N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 42

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Volatile and Non Volatile Registers
6.5.3
6.5.4
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The Erase Suspend Status should be considered valid when the P/E Controller bit is high
(FSR<7>=1).
When a Program/Erase Resume command (PER) is issued the Erase Suspend Status bit
returns Low (FSR<6>=0)
Erase Status bit
The bit 5 of the Flag Status Register represents the Erase Status bit. It indicates an erase
failure or a protection error when an erase operation is issued.
When the Erase Status bit is High (FSR<5>=1) after an Erase failure that means that the
P/E Controller has applied the maximum pulses number to the portion to be erased and still
failed to verify that it has correctly erased.
The Erase Status bit should be read once the P/E Controller Status bit is High.
The Erase Status bit is related to all possible erase operations: Sector Erase, Sub Sector
Erase, and Bulk Erase in all the three available protocols (SPI, DIO-SPI and QIO-SPI).
Once the bit 5 is set High, it can only be reset Low (FSR<5>=0) by a Clear Flag Status
Register command (CLFSR).
If set High it should be reset before a new Erase command is issued; otherwise the new
command will appear to fail.
Program Status bit
The bit 4 of the Flag Status Register represents the Program Status bit. It indicates:
When the Program Status bit is High (FSR<4>=1) after a Program failure that means that
the P/E Controller has applied the maximum pulses number to the bytes and it still failed to
verify that the required data have been correctly programmed.
After an attempt to program '1' on '0', the FSR<4> only goes High (FSR<4>=1) if
VPP=VPPH and the data pattern is a multiple of 64 bits: if VPP is not VPPH, FSR<4>
remains Low and the attempt is not shown while if VPP is equal to VPPh but the pattern is
not a 64 bits multiple the bit 4 is Don't Care. The Program Status bit should be read once the
P/E Controller Status bit is High.
The Program Status bit is related to all possible program operations in the Extended SPI
protocol: Page Program, Dual and Quad Input Fast Program, Dual and Quad Input
Extended Fast Program, and OTP Program.
The Program Status bit is related to the following program operations in the DIO-SPI and
QIO-SPI protocols: Dual and Quad Command Page program and OTP program.
Once the bit is set High, it can only be reset Low (FSR<4>=0) by a Clear Flag Status
Register command (CLFSR). If set High it should be reset before a new Program command
is issued, otherwise the new command will appear to fail.
a Program failure
an attempt to program a '1' on '0' when VPP=VPPH (only when the pattern is a multiple
of 64 bits, otherwise this bit is "Don't care").
a protection error when a program is issued
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q064 - 3 V