N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 109

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
9.3.5
DQ0
DQ3
DQ1
DQ2
C
S
Figure 75. Read OTP instruction and data-out sequence QIO-SPI
Write Enable (WREN)
The Write Enable (WREN) instruction sets the Write Enable Latch (WEL) bit. Apart form the
parallelizing of the instruction code on the four pins DQ0, DQ1, DQ2 and DQ3, the
instruction functionality is exactly the same as the Write Enable instruction of the Extended
SPI protocol, please refer to
Figure 76. Write Enable instruction sequence QIO-SPI
Instruction
0
1
5
4
6
7
2
DQ0
DQ1
DQ3
DQ2
S
C
1
0
2
3
3
5
4
6
7
4
Section 9.1.10: Write Enable (WREN)
1
0
2
3
5
5
4
6
7
6
Instruction
1
0
2
3
7
0
Quad_Write_Enable
8
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1
9 10
Dummy (ex.: 10)
15 16 17 18
5
4
6
7
out 1
Data
1
19
0
3
2
©2010 Micron Technology, Inc. All rights reserved.
20
5
4
7
out n
6
Data
for further details.
21
1
0
3
2
22
4
5
7
6
23
0
1
3
2
Instructions
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