N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 36

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

Volatile and Non Volatile Registers
6.2.5
6.2.6
6.3
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Quad Input NV configuration bit (NVCR bit 3)
The Quad Input NV configuration bit can be used to make the memory start working in QIO-
SPI protocol directly after the power on sequence. The products are delivered with this set
to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0
the device will enter in QIO-SPI protocol right after the next power on.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the
Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.
Dual Input NV configuration bit (NVCR bit 2)
The Dual Input NV configuration bit can be used to make the memory start working in DIO-
SPI protocol directly after the power on sequence. The products are delivered with this set
to 1, making the memory default in Extended SPI protocol, if the application sets this bit to 0
the device will enter in QIO-SPI protocol right after the next power on.
Please note that in case both QIO-SPI and DIO-SPI are enabled (both bit 3 and bit 2 of the
Non Volatile Configuration Register set to 0), the memory will work in QIO-SPI.
Volatile Configuration Register
The Volatile Configuration Register (VCR) affects the memory configuration after every
execution of Write Volatile Configuration Register (WRVCR) instruction: this instruction
overwrite the memory configuration set at POR by the Non Volatile Configuration Register
(NVCR). Its purpose is to define the dummy clock cycles number and to make the device
ready to enter in the required XIP mode.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2010 Micron Technology, Inc. All rights reserved.
N25Q064 - 3 V