N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 127

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
10.1
Table 23.
(WRNVCR
opcode)
B1h
Yes
XiP Confirmation
Is XIP enabled ?
NVCR Check
Power On
XIP mode
6 dummy cycles
bit = 0 ?
Figure 99. N25Q064 Read functionality Flow Chart
Enter XIP mode by setting the Non Volatile Configuration
Register
To use the Non Volatile Configuration Register method to enter in XIP mode it is necessary
to set the Non Volatile Configuration Register bits from 11 to 9 with the pattern
corresponding to the required XIP mode by mean of the Write Non Volatile Configuration
Register (WRNVCR) instruction. (See
This instruction doesn't affect the XIP state until the next Power on sequence. In this case,
after the next power on sequence, the memory directly accept addresses and then, after the
dummy clock cycles (configurable), outputs the data as described in
bits setting
dummy clock cycles the following pattern must be issued:
NVCR XIP bits setting example
for fast read
instructions
+ 0110
Yes
No
example. For example to enable XIP on QIOFR in normal SPI protocol with six
No
SPI standard mode (no
100
XiP, VCR <3> = 1)
111
Table 23.: NVCR XIP bits setting
Micron Technology, Inc., reserves the right to change products or specifications without notice.
VCR<3> = 0 ?
x
No
Yes
No
1
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SPI mode (no XIP) but
Read Instructions ?
Table 23.: NVCR XIP
ready to enter XIP
XiP Confirmation
example.)
bit = 0 ?
XIP Operations
11
Yes
Yes
127/150
No
xx