N25Q064A13EF640F Micron Technology Inc, N25Q064A13EF640F Datasheet - Page 113

• Manufacturer Part Number: N25Q064A13EF640F
• Manufacturer: Micron Technology Inc

Specifications of N25Q064A13EF640F

• Lead Free Status / Rohs Status: Supplier Unconfirmed

N25Q064 - 3 V
9.3.9
9.3.10
Subsector Erase (SSE)
The Subsector Erase (SSE) instruction sets to '1' (FFh) all bits inside the chosen subsector.
Before it can be accepted, a Write Enable (WREN) instruction must previously have been
executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Subsector Erase
(SSE) instruction of the Extended SPI protocol, please refer to
Erase (SSE)
Figure 82. Subsector Erase instruction sequence QIO-SPI
Sector Erase (SE)
The Sector Erase (SE) instruction sets to '1' (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
Apart form the parallelizing of the instruction code and the address on the four pins DQ0,
DQ1, DQ2 and DQ3, the instruction functionality is exactly the same as the Sector Erase
(SE) instruction of the Extended SPI protocol, please refer to
(SE)
for further details.
for further details.
DQ0
DQ2
*Address bit A23 is “Don’t Care. ”
DQ1
DQ3
S
C
Instruction
0
1
2
20 16 12 8
21 17 13 9
22 18 14 10
23 19 15 11
24-Bit Address*
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
4
5
6
5
6
4
7
7
2
0
1
3
8
9
Section 9.1.19: Sector Erase
Section 9.1.18: Subsector
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Instructions
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