DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 84

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register Name:
Register Description: Transmit HDLC Channel Definition
Register Address:
Note: Bits that are underlined are read only, all other bits are read-write.
Bit 0 / Transmit Transparent Enable (TTRANS). When this bit is set low, the HDLC engine will
generate flags and the FCS (if enabled via TCRC0/1) and perform zero stuffing. When this bit is set high,
the HDLC engine does not generate flags or the FCS and does not perform zero stuffing.
Bit 1 / Transmit Interfill Select (TIFS).
Bit 2 & Bit 3 / Transmit CRC Selection (TCRC0/TCRC1). These 2 bits are ignored if the HDLC
channel is set into Transparent mode (TTRANS = 1).
Bit 4 / Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are
not inverted after being generated. When this bit is set high, the HDLC engine inverts all the data (flags,
information fields, and FCS) after the packet has been generated.
Bit 5 / Transmit Bit Flip (TBF). When this bit is set low, the HDLC engine will obtain the first HDLC
bit to be transmitted from the lowest bit position of the PCI Bus bytes (i.e. PAD[0] / PAD[8] / PAD[16] /
PAD[24]). When this bit is set high, the HDLC engine will obtain the first HDLC bit to be transmitted
from the highest bit position of the PCI Bus bytes (i.e. PAD[7] / PAD[15] / PAD[23] / PAD[31]).
TABTE
n/a
15
7
0 = transparent mode disabled
1 = transparent mode enabled
0 = the interfill byte is 7Eh (01111110)
1 = the interfill byte is FFh (11111111)
TCRC1
0
0
1
1
0 = do not invert data
1 = invert all data (including flags and FCS)
0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the
PCI Bus
1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the
PCI Bus
TCFCS
n/a
14
6
TCRC0
0
1
0
1
THCD
0484h
TBF
n/a
13
5
Action
no CRC is generated
16-bit CRC (CCITT/ITU Q.921)
32-bit CRC
illegal state
TZSD
TID
12
4
TCRC1
84 of 203
TFG3
11
3
TCRC0
TFG2
10
2
TFG1
TIFS
1
9
TTRANS
TFG0
0
8
DS3134