DS3134 Maxim Integrated Products, DS3134 Datasheet
DS3134
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DS3134 Summary of contents
Page 1
... Onboard Bit Error Rate Tester (BERT) with auto error insertion capability DESCRIPTION The DS3134 Chateau device is a 256-channel HDLC controller. The DS3134 is capable of handling data streams data streams. Each of the 16 physical ports can handle one, two or four data streams. The Chateau consists of the following blocks: ...
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... The device fully meets the following specifications: ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 and PCI Local Bus Specification V2.1 June 1, 1995. ITU Q.921 March 1993 and ISO Standard 3309-1979 Data Communications – HDLC Procedures – Frame Structure 203 DS3134 ...
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... Removed bit 1 of the RDMAQ register, this function is automatically implemented. Please refer to section 8.1.3 (page 90) 5. Figure 10.3A signal LRD* is moved back one LCLK cycle to align with the rising edge of LCLK #1. 6. Figure 103B signal LWR* is moved back one LCLK cycle to align with the rising edge of LCLC # 203 DS3134 ...
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... Local Bus timing update, corrected t3 and t6 on page 169. 7. Change the number of T1/E1 support from 56 back to 64 (Section 1), this will be supported in the next rev of silicon. 8. Added a product preview page. Version 7 (09/15/00) 1. Update figure 9.1C. 2. Update figure 14C in Section 14. 3. Typo correction 203 DS3134 ...
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... General Description……………………………………………………………………….. 6.2 HDLC Register Description……………………………………………………………… 203 DS3134 32 34 ...
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... Section 13: Mechanical Dimensions…………………………………………………………………….173 Section 14: Applications……………………………………………………………………………… 174 6 of 203 DS3134 85 87 ...
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... SECTION 1: INTRODUCTION The DS3134 Chateau device is a 256 channels HDLC controller. The primary features of the device are listed in Table 1A. This data sheet is split in Sections along the major the blocks of the device as shown in Figure 1A. Throughout the data sheet, certain terms will be used and these terms are defined in Table 1B ...
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... DS3134 FEATURE LIST Table 1A Layer Can Support Data Streams or Two T3 Data Streams One 16 Independent Physical Ports all Capable of Speeds MHz Two of These Ports are also Capable of Speeds MHz Each Port can be Independently Configured for Either Channelized or Unchannelized Operation Each Physical Channelized Port can Handle One, Two, or Four Data Streams Supports kbps and kbps Onboard V ...
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... In Bridge Mode; can arbitrate for the Bus Bits Wide In Bridge Mode, Supports a 1M Byte Address Space Supports both Intel and Motorola Bus Timing JTAG TEST ACCESS 3.3V LOW POWER CMOS WITH 5V TOLERANT INPUTS AND OUTPUTS 256 LEAD PLASTIC BGA PACKAGE ( MM 203 DS3134 ...
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... GENERAL DESCRIPTION The Layer One Block handles the physical input and output of serial data to and from the DS3134. The DS3134 is capable of handling data streams data streams. Each of the 16 physical ports can handle up to two or four data streams. Section 14 contains some examples of how this is performed ...
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... FIFO and then the FIFO decides which HDLC channel gets the highest priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS3134 can handle multiple HDLC channels quite possible that at any one time, several HDLC channels will need the DMA to burst data from the PCI Bus into the FIFO ...
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... Configuration Bus in which case bus slave. The Bridge Mode allows the Host on the PCI Bus to access the local bus. The DS3134 will map data from the PCI Bus to the local bus. In the Configuration Mode, the local bus is used only to control and monitor the DS3134 while the HDLC packet data will still be transferred to the Host via the PCI Bus ...
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... DS3134 RESTRICTIONS FOR REV B1/B2 SILICON Table 1D Port maximum of 16 channelized and unchannelized physical ports Unchannelized ports 0 & 1: maximum data rate of 52 Mbps port 2 to 15: maximum data rate of 10 Mbps Channelized Channelized and with frame interleave interfaces or a minimum of two/multiple of two consecutive DS0 time slot assigned to one ...
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... RAMs, the HDLC Configuration registers, and the FIFO registers) are not affected by a system reset and they must be configured on power-up by the Host to a proper state. Figure 1B lists the ordered steps to initialize the DS3134. Note: After device power up and reset, it takes 0.625 mS to get a port up and operating. In other words, the ports must have wait a minimum of 0 ...
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... HDLC Channel) 256 (one for each HDLC Channel) 1024 (one for each FIFO Block) 256 (one for each HDLC Channel) 256 (one for each HDLC Channel) 1024 (one for each FIFO Block) 256 (one for each HDLC Channel 203 DS3134 ...
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... SECTION 2: SIGNAL DESCRIPTION 2.1 OVERVIEW / SIGNAL LEAD LIST This section describes the input and output signals on the DS3134. Signal names follow a convention that is shown in Table 2.1A. Table 2.1B lists all of the signals, their signal type, description, and lead location. Signal Naming Convention Table 2.1A ...
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... No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead. No Connect. Do not connect any signal to this lead 203 DS3134 ...
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... PCI Bus Command / Byte Enable Bit 2. PCI Bus Command / Byte Enable Bit 3. PCI & System Clock. A 25MHz to 33 MHz clock is applied here. PCI Device Select. PCI Cycle Frame. PCI Bus Grant. PCI Initialization Device Select. PCI Interrupt. PCI Initiator Ready. PCI Bus Parity 203 DS3134 ...
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... Receive Serial Data for Port 12. Receive Serial Data for Port 13. Receive Serial Data for Port 14. Receive Serial Data for Port 15. Receive Serial Sync for Port 0. Receive Serial Sync for Port 1. Receive Serial Sync for Port 2. Receive Serial Sync for Port 203 DS3134 ...
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... Transmit Serial Data for Port 9. Transmit Serial Data for Port 10. Transmit Serial Data for Port 11. Transmit Serial Data for Port 12. Transmit Serial Data for Port 13. Transmit Serial Data for Port 14. Transmit Serial Data for Port 15. Test. Factory tests signal; leave open circuited 203 DS3134 ...
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... Positive Supply. 3.3V (+/- 10%). Positive Supply. 3.3V (+/- 10%). Positive Supply. 3.3V (+/- 10%). Positive Supply. 3.3V (+/- 10%). Positive Supply. 3.3V (+/- 10%). Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference. Ground Reference 203 DS3134 ...
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... MHz mode) RC clocks acceptable to only pulse the RS signal once to establish byte boundaries and allow Chateau to keep track of the byte/frame boundaries by counting RC clocks. If the incoming data does not require alignment to byte/frame boundaries, then this signal should be tied low. Signal Description Ground Reference. Ground Reference. Ground Reference. Ground Reference 203 DS3134 ...
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... Normal TC Clock Mode Inverted TC Clock Mode falling edge rising edge falling edge falling edge 23 of 203 DS3134 rising edge falling edge rising edge rising edge rising edge falling edge rising edge rising edge ...
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... Local Bus, these signals will be outputs that are updated on the rising edge of LCLK. When writing data to the Local Bus, these signals will become inputs which will be sampled on the rising edge of LCLK. In the Configuration Mode, only the 16-bit bus width is allowed (i.e. byte addressing is not available 203 DS3134 ...
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... If not used in the PCI Bridge Mode, this signal should be tied high. In the Configuration Mode (LMS = 1) this signal is an open drain output which will be forced low if one or more unmasked interrupt sources within the device is active. The signal will remain low until the interrupt is either serviced or masked 203 DS3134 ...
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... Local Bus is not currently involved in a bus transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal will remain in tri-state when the Local Bus is not currently involved in a bus transaction and when the Local Bus is in the Configuration Mode (LMS = 1 203 DS3134 ...
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... This action will set the device into the boundary scan bypass mode allowing normal device operation. If boundary scan is not used, this signal should be held low. This signal has an internal pull-up. This output is tri-stated when the Local Bus is in the 27 of 203 DS3134 ...
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... PCLK. When the device is a target, this signal is input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, these signals are tri-stated. Signal Name: PPAR 28 of 203 DS3134 ...
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... PCLK. When the device is an initiator, this signal is input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction, PTRDY* is tri-stated. This signal handshakes with the PTRDY* signal during a bus 29 of 203 DS3134 ...
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... Signal Name: PPERR* Signal Description: PCI Parity Error Signal Type: Input / Output (tri-state capable) This active low signal reports parity errors that occur. PPERR* can be enabled and disabled via the PCI Configuration Registers. This signal is updated on the rising edge of PCLK 203 DS3134 ...
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... This active low signal is asserted on the same clock edge as PFRAME* is deasserted and is deasserted on the same clock edge as PIRDY* is deasserted. This signal will only be asserted when the device is an initiator. This signal is an output and is updated on the rising edge of PCLK 203 DS3134 ...
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... This input should be left open circuited by the user. Signal Name: VDD Signal Description: Positive Supply Signal Type: n/a 3.3V (+/- 10%). All VDD signals should be tied together. Signal Name: VSS Signal Description: Ground Reference Signal Type: n/a All VSS signals should be tied to the local ground plane 203 DS3134 ...
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... Status Register for DMA. Interrupt Mask Register for SDMA. Status Register for V.54 Loopback Detector. Interrupt Mask Register for SV54. Local Bus Bridge Mode Control Register. Test Register 203 DS3134 PCI Host Local Bus Host (16-bit address) (0x000) (00xx) (0x1xx) (01xx) ...
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... Transmit Port 8 Control Register. Transmit Port 9 Control Register. Transmit Port 10 Control Register. Transmit Port 11 Control Register. Transmit Port 12 Control Register. Transmit Port 13 Control Register. Transmit Port 14 Control Register. Transmit Port 15 Control Register 203 DS3134 Section 5.2 5.2 5.2 5.2 5.2 5.2 5.2 5 ...
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... Channelized Port 15 Register Data. Register Name Receive HDLC Channel Definition Indirect Select. Receive HDLC Channel Definition. Receive HDLC maximum Packet Length. One per Device Transmit HDLC Channel Definition Indirect Select. Transmit HDLC Channel Definition 203 DS3134 Section 5.3 5.3 5.3 5.3 5.3 5.3 5 ...
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... Receive Descriptor Base Address 0 (lower word). Receive Descriptor Base Address 1 (upper word). Receive DMA Configuration Indirect Select. Receive DMA Configuration. Receive DMA Queues Control. Receive Large Buffer Size. Receive Small Buffer Size 203 DS3134 Section 5.6 5.6 5.6 5.6 5.6 5.6 5 ...
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... PCI Vendor ID / Device ID 0. PCI Command Status 0. PCI Revision ID / Class Code 0. PCI Cache Line Size / Latency Timer / Header Type 0. PCI Device Configuration Memory Base Address. PCI Interrupt Line & Pin / Min. Grant / Max. Latency 203 DS3134 Section 8.2.3 8.2.3 8.2.3 8.2.3 8.2.3 8 ...
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... PCI Vendor ID / Device ID 1. PCI Command Status 1. PCI Revision ID / Class Code 1. PCI Cache Line Size / Latency Timer / Header Type 1. PCI Device Local Base Memory Base Address. PCI Interrupt Line & Pin / Min. Grant / Max. Latency 203 DS3134 Section 9.2 9.2 9.2 9.2 9.2 ...
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... Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits n/a n/a n ID4 ID3 ID2 TDT0 TDE RDT1 RFPC0 BPS4 BPS3 39 of 203 DS3134 1 0 n/a RST 9 8 ID1 ID0 1 0 RDT0 RDE 9 8 BPS2 BPS1 ...
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... HDLC data on the PCI Bus. All other PCI Bus transactions to the internal device configuration registers, PCI configuration registers, and Local Bus, are always in Little Endian format HDLC Packet Data on the PCI Bus is in Little Endian format 1 = HDLC Packet Data on the PCI Bus is in Big Endian format 40 of 203 DS3134 ...
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... All status remains active even if the associated Interrupt is disabled. 10000 = Port 0 (hi speed) 10001 = Port 1 (hi speed) 10010 = n/a 10011 = n/a 10100 = n/a 10101 = n/a 10110 = n/a 10111 = n 203 DS3134 11000 = n/a 11001 = n/a 11010 = n/a 11011 = n/a 11100 = n/a 11101 = n/a 11110 = n/a 11111 = n/a ...
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... The Host can determine which specific HDLC channel incurred a FIFO overflow/underflow, CRC error, octet length error or abort by reading the status bits as reported in Done Queues which are created by the DMA. There are no control bits to stop these events from being reported in the SDMA register 203 DS3134 ...
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... Port #14 Port #15 Transmit Receive Port I Port I TCOFA RCOFA TP0CR Bit # #13 #14 #15 OR PPERR PSERR n/a SBERT SLBP5 SLBP4 SLBP3 SLBP2 Change in V.54 Detector (SLBP) Port # 203 RP0CR Bit # #13 #14 # COFA COFA SLBP1 SLBP0 Change in V.54 Detector (SLBP) Port #0 DS3134 ...
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... PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode. This status bit is also reported in the Control/Status register in the PCI Configuration registers, see Section 9 for more details PPERR PSERR SBERT n/a n/a n 203 DS3134 1 0 STCOFA SRCOFA 9 8 n/a n/a ...
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... Bit 1 / Status Bit for Transmit Change Of Frame Alignment (STCOFA interrupt masked 1 = interrupt unmasked Bit 2 / Status Bit for Change of State in BERT (SBERT interrupt masked 1 = interrupt unmasked PPERR PSERR SBERT n/a n/a n 203 DS3134 1 0 STCOFA SRCOFA 9 8 n/a n/a ...
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... PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode. See Section 5 for specific details on the operation of the V.54 loopback detector SLBP4 SLBP3 SLBP2 SLBP12 SLBP11 SLBP10 46 of 203 DS3134 1 0 SLBP1 SLBP0 9 8 SLBP9 SLBP8 ...
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... If enabled via the RLENC bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit SLBP4 SLBP3 SLBP2 SLBP12 SLBP11 SLBP10 RLENC RABRT RCRCE TUDFL RDQWE RDQW 47 of 203 DS3134 1 0 SLBP1 SLBP0 9 8 SLBP9 SLBP8 1 0 n/a n RSBRE RSBR ...
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... Done Queue has occurred. If enabled via the RDQW bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode 203 DS3134 ...
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... If enabled via the TDQWE bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode 203 DS3134 ...
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... Bit 9 / Status Bit for Receive DMA Small Buffer Read Error (RSBRE interrupt masked 1 = interrupt unmasked Bit 10 / Status Bit for Receive DMA Done Queue Write (RDQW interrupt masked 1 = interrupt unmasked RLENC RABRT RCRCE TUDFL RDQWE RDQW 50 of 203 DS3134 1 0 n/a n RSBRE RSBR ...
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... Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0. Bit 0 / Factory Test (FT). This bit is used by the factory to place the DS3134 into the test mode. For normal device operation, this bit should be set to zero whenever this register is written to. Setting this bit places the RAMs into a low power standby mode ...
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... SECTION 5: LAYER ONE 5.1 GENERAL DESCRIPTION The Layer One Block is shown in Figure 5.1A. Each of the 16 Layer One ports on the DS3134 can be configured to support either a channelized application or an unchannelized application. Users can mix the applications on the ports as needed. Some or all of the ports can be channelized while the others can be configured as unchannelized ...
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... The BERT function is a shared resource among the 16 ports on the DS3134 and it can only be assigned to one port at a time. The BERT function can be used in both channelized and unchannelized applications and at speeds MHz ...
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... Local Network UNLB Sec. Loop- Loop- 5.3) Back Back (CLLB) (CNLB) Transmit Un- Channel- ized Network Loopback (UNLB) BERT Mux (see Figure 5.5A 203 SLOW To / HDLC From (One per FIFO Port) Block Ports 0 & 1 Only FAST HDLC l1_bd DS3134 ...
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... RS[n] / TS[n] 1/2 Clock Early & Inverted RS[n] / TS[n] 1 Clock Early & Not Inverted RS[n] / TS[n] 2 Clocks Early & Not Inverted Bit 192 or 255 Bit 0 or 511 or 1023 Last Bit of First Bit of the Frame the Frame tdm_tim 55 of 203 DS3134 Bit 1 ...
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... RSD0 VRST RISE VTO n/a LLB 56 of 203 DS3134 1 0 RIDE RICE 9 8 RUEN RP[i]HS ...
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... V.54 loop down pattern is seen or the V.54 detector is reset by the Host (i.e. by toggling VRST). See Section 5.4 for more details on how the V.54 detector operates. Bit 14 / Interrupt Enable for RCOFA (IERC interrupt masked 1 = interrupt enabled 57 of 203 DS3134 ...
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... TSD0 TFDA1* TISE n/a TUBS UNLB 58 of 203 DS3134 1 0 TIDE TICE 9 8 TUEN TP[i]HS ...
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... Alignment is detected. A COFA is detected by sensing that a sync pulse has occurred during a clock period that was not the first bit of the 193/256/512/1024 bit frame. This bit will be reset when read and it will not be set again until another COFA has occurred. When enabled, this bit forces the port to operate 203 DS3134 ...
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... T1, E1, 4.096 MHz, or 8.192 MHz mode. 0000000 (00h) = DS0 Channel Number 0 1111111 (7Fh) = DS0 Channel Number 127 RV54 n/a CLLB n/a CNLB n CHID4 CHID3 CHID2 n/a n/a n 203 DS3134 lsb lsb n/a R56 lsb TFAO T56 1 0 CHID1 CHID0 9 8 CPRS1 CPRS0 ...
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... During a read operation, this bit will be set to a one until the data is ready to be read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set to a one while the write is taking place. It will be set to zero once the write operation has completed 203 DS3134 DS0 Channels Available 0 ...
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... Port RAM (one each for all 16 Ports 15) C[n]DAT126 C[n]DAT127 4 3 CHD4 CHD3 CHD2 CHD12 CHD11 CHD10 C[n]DAT0 R[n]CFG0 C[n]DAT1 R[n]CFG1 C[n]DAT2 R[n]CFG2 C[n]DAT3 R[n]CFG3 C[n]DAT4 R[n]CFG4 ... ... R[n]CFG126 R[n]CFG127 62 of 203 CHD1 CHD0 9 8 CHD9 CHD8 T[n]CFG0 T[n]CFG1 T[n]CFG2 T[n]CFG3 T[n]CFG4 ... T[n]CFG126 T[n]CFG127 DS3134 ...
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... HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0) 00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1) 00000010 (02h) = HDLC Channel Number 3 11111111 (FFh) = HDLC Channel Number 256 RV54 n/a CLLB 63 of 203 DS3134 n/a R56 ...
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... T[n]CFG[j] where for each Port & 127 for each DS0 Register Description: Transmit Layer 1 Configuration Register Register Address: Indirect Access via CP[n] TCH#(8): Transmit HDLC Channel Number TCHEN TBERT n/a Note: Bits that are underlined are read only, all other bits are read-write n/a CNLB n 203 DS3134 TFAO T56 ...
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... In order for the data to make it from the BERT block, the Host must also configure the BERT for the proper port via the Master Control register (see Section 4). This bit overrides TFAO and TCHEN not route data from BERT 1 = route data from BERT (override the data from the HDLC controller 203 DS3134 ...
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... DS0 channels should be searched for the V.54 pattern. In channelized applications, it may be that there will be multiple HDLC channels that the Host wishes to look for the V.54 pattern in. If this is true, then the Host will perform the routine shown in Table 5.4A. A flowchart of the same routine is shown in Figure 5. 203 DS3134 ...
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... If VLB = 0, if the DS0 channels are already in loopback, then the Host will monitor VLB to know when the loop down pattern has been detected and hence when to take the channels out of loopback. The DS0 channels are taken out of loopback by again configuring the CNLB bits. Move on to Step # 203 DS3134 ...
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... DS0 channels can be placed into loopback via the Receive Layer 1 Configuration Register (see Section 5.3) SLBP is a status bit that is reported in the SV54 register (see Section 4.3) DS0 channels can be taken out of loopback via the Receive Layer 1 Configuration Register (see Section 5. 203 DS3134 ...
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... All Ones SLBP = 1 Search for Loop Down Pattern VLB = 1 Sync = 1 wait for Loss of Sync or All 1s ( Row) All Ones VLB = 0 SLBP = 203 Time Out (VTO) Loopback (VLB); both in RP[n]CR Change of State in Status (SLBP); in SV54 Sync = 0 Sync = 0 v54sm DS3134 ...
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... Block Internal Control & Configuration Bus bertbd Port 0 (slow) Port 1 (slow) Port 2 (slow) Port 3 (slow) Port 4 (slow) BERT Port 5 (slow) Mux Port 13 (slow) Port 14 (slow) Port 15 (slow) Port 0 (fast) Port 1 (fast) BERT Select (5) In the Master Configuration Register 70 of 203 DS3134 ...
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... BERT Repetitive Pattern Set BERT Repetitive Pattern Set BERT 32-Bit Bit Counter BERT 32-Bit Bit Counter RLOS BED BBCO BERT 24-Bit Error Counter 71 of 203 lsb LC RESYNC RPL1 RPL0 lsb n/a n/a TC lsb lsb lsb lsb lsb BECO SYNC lsb DS3134 ...
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... Bit 8 / Repetitive Pattern Length Bit 0 (RPL0). Bit 9 / Repetitive Pattern Length Bit 1 (RPL1). Bit 10 / Repetitive Pattern Length Bit 2 (RPL2 PS2 PS1 PS0 n/a RPL3 RPL2 A low to high transition will force the receive BERT 72 of 203 DS3134 RESYNC 9 8 RPL1 RPL0 ...
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... Must be cleared and set again for a subsequent loads. Code Length Code 0001 19 Bits 0010 0101 23 Bits 0110 1001 27 Bits 1010 1101 31 Bits 1110 SBE n/a n Alternating Word Count 73 of 203 DS3134 Length Code 20 Bits 0011 24 Bits 0111 28 Bits 1011 32 Bits 1111 ...
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... Register Address: 050Ch BERTRP0: BERT Repetitive Pattern Set 0 (lower word BERT Repetitive Pattern Set (lower byte Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits BERT Repetitive Pattern Set 74 of 203 DS3134 ...
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... BERTBC1: BERT Bit Counter 0 (upper word BERT 32-Bit Bit Counter (upper byte) Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits BERT Repetitive Pattern Set BERT 32-Bit Bit Counter 20 19 BERT 32-Bit Bit Counter 203 DS3134 ...
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... Bit 6 / Receive All Ones (RA1). A latched bit which is set when 31 consecutive ones are received. Allowed to be cleared once a zero is received. Bits BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the BERTEC1 register description for details RLOS BED BBCO 203 DS3134 1 0 BECO SYNC 9 8 ...
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... BERT loses synchronization. This counter will be loaded with the current bit count value when the LC control bit in the BERTC0 register is toggled from a low ( high (1). When full, this counter will saturate and set the BECO status bit BERT 24-Bit Error Counter 203 DS3134 ...
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... SECTION 6: HDLC 6.1 GENERAL DESCRIPTION The DS3134 contains two different types of HDLC controllers. Each port has a Slow HDLC Engine (type #1) associated with it that can operate in either a channelized mode up to 8.192 Mbps or an unchannelized mode at rates Mbps. Ports 0 and 1 also have associated with them, an additional Fast HDLC Engine (type #2) that is capable of operating in only an unchannelized fashion Mbps ...
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... The first bit received becomes either the LSB (normal mode) or the MSB (telecom mode) of the byte stored in the FIFO. - Also available in the transparent mode. Transparent Mode - If enabled, flag detection, zero destuffing, abort detection, length checking, and FCS checking are disabled. - Data is passed to the PCI Bus on octet (i.e. byte) boundaries in channelized operation 203 DS3134 ...
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... HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0) 00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1) 00000010 (02h) = HDLC Channel Number 3 11111111 (FFh) = HDLC Channel Number 256 HCID4 HCID3 HCID2 n/a n/a n 203 DS3134 1 0 HCID1 HCID0 9 8 n/a n/a ...
Page 81
... This bit is ignored if the HDLC channel is set into Transparent mode (RTRANS = 1 octet length detection disabled 1 = octet length detection enabled RID RCRC1 RCRC0 n/a n/a n 203 DS3134 1 0 ROLD RTRANS 9 8 n/a RZDD ...
Page 82
... When this bit is set high, the HDLC engine will not zero destuff the incoming data stream. This bit is ignored when the HDLC engine is configured in the Transparent Mode (RTRANS = 1). Action no CRC verification performed 16-bit CRC (CCITT/ITU Q.921) 32-bit CRC illegal state 82 of 203 DS3134 ...
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... It will be set to zero once the write operation has completed RHPL4 RHPL3 RHPL2 RHPL12 RHPL11 RHPL10 HCID4 HCID3 HCID2 n/a n/a n 203 DS3134 1 0 RHPL1 RHPL0 9 8 RHPL9 RHPL8 1 0 HCID1 HCID0 9 8 n/a n/a ...
Page 84
... HDLC bit transmitted is obtained from the highest bit position of the bytes on the PCI Bus TID TCRC1 TCRC0 TZSD TFG3 TFG2 Action no CRC is generated 16-bit CRC (CCITT/ITU Q.921) 32-bit CRC illegal state 84 of 203 DS3134 1 0 TIFS TTRANS 9 8 TFG1 TFG0 ...
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... DS3134 ...
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... As long as the maximum throughput rate of 104 Mbps is not exceeded, the DS3134 has been designed to insure that there is enough bandwidth in this transfer to prevent any loss of data in between the HDLC Engines and the FIFO ...
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... Block 124 not used Block 125 Channel 2 Block 126 Channel 2 Block 127 not used Block 1022 not used Block 1023 not used 87 of 203 DS3134 Block Pointer RAM not used Block 0 not used Block 1 Block 4 Block 2 Block 5 Block 3 Block 3 Block 4 Block 2 ...
Page 88
... Register Description: Receive FIFO Starting Block Pointer Indirect Select Register Address: 0900h HCID7 HCID6 HCID5 IAB IARW n/a Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits HCID4 HCID3 HCID2 n/a n/a n 203 DS3134 1 0 HCID1 HCID0 9 8 n/a n/a ...
Page 89
... Note: The RFSBP is a write only register. Once this register has been written to and operation started, DS3134 internal state machine will change the value in this register. Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only bit will be set to a one ...
Page 90
... Block 511 is the Next Linked Block 1111111111 (3FFh) = Block 1023 is the Next Linked Block Register Name: RFHWMIS BLKID4 BLKID3 BLKID2 n/a n/a n RBP4 RBP3 RBP2 n/a n/a n 203 DS3134 1 0 BLKID1 BLKID0 9 8 BLKID9 BLKID8 1 0 RBP1 RBP0 9 8 RBP9 RBP8 ...
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... N = number of blocks are linked together. Any other numbers are illegal. 0000000000 (000h) = invalid setting 0000000001 (001h) = High Water Mark is 1 Block HCID4 HCID3 HCID2 n/a n/a n RHWM4 RHWM3 RHWM2 n/a n/a n 203 DS3134 1 0 HCID1 HCID0 9 8 n/a n RHWM1 RHWM0 9 8 RHWM9 RHWM8 ...
Page 92
... Note: The TFSBP is a write only register. Once this register has been written to and operation started, DS3134 internal state machine will change the value in this register. Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only bit will be set to a one ...
Page 93
... It will be set to zero when the data is ready to be read. During a write operation, this bit will be set to a one while the write is taking place. It will be set to zero once the write operation has completed BLKID4 BLKID3 BLKID2 n/a n/a n 203 DS3134 1 0 BLKID1 BLKID0 9 8 BLKID9 BLKID8 ...
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... It will be set to zero when the data is ready to be read. During a write operation, this bit will be set to a one while the write is taking place. It will be set to zero once the write operation has completed TBP4 TBP3 TBP2 n/a n/a n HCID4 HCID3 HCID2 n/a n/a n 203 DS3134 1 0 TBP1 TBP0 9 8 TBP9 TBP8 1 0 HCID1 HCID0 9 8 n/a n/a ...
Page 95
... Low Water Mark is 1 Block 0000000010 (002h) = Low Water Mark is 2 Blocks 0111111111 (1FFh) = Low Water Mark is 511 Blocks 1111111111 (3FFh) = Low Water Mark is 1023 Blocks TLWM4 TLWM3 TLWM2 n/a n/a n 203 DS3134 1 0 TLWM1 TLWM0 9 8 TLWM9 TLWM8 ...
Page 96
... The receive and transmit Packet Descriptors have almost identical structures (see Sections 8.1.2 and 8.2.2) which provides a minimal amount of Host intervention in store-and-forward applications. In other words, the receive descriptors created by the receive DMA can be used directly by the transmit DMA. The receive and transmit portions of the DMA are completely independent and will be discussed separately 203 DS3134 ...
Page 97
... Transmit Done Queue FIFO Flush Timer. Transmit Descriptor Base Address 0 (lower word). Transmit Descriptor Base Address 1 (upper word). Transmit DMA Configuration Indirect Select. Transmit DMA Configuration (all 256 channels). Transmit Queues FIFO Control 203 DS3134 Section 8.1.3 8.1.3 8.1.3 8.1.3 8.1.3 8 ...
Page 98
... Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits LBS4 LBS3 LBS2 LBS12 LBS11 LBS10 SBS4 SBS3 SBS2 SBS12 SBS11 SBS10 98 of 203 DS3134 1 0 LBS1 LBS0 9 8 LBS9 LBS8 1 0 SBS1 SBS0 9 8 SBS9 SBS8 ...
Page 99
... A dedicated area of memory that the Host will write to inform the DMA where to store incoming packet data. A dedicated area of memory that the DMA will write to inform the Host that the packet data is ready for processing 203 DS3134 ...
Page 100
... The Host then reads the Next Descriptor Pointer in the link listed chain and continues this process until either a number (from descriptors have been processed or an end of packet has been reached. 6. The Host then checks the Done Queue Descriptor circular queue to see if any more data buffers are ready for processing. 100 of 203 DS3134 ...
Page 101
... Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #2 Data Buffer Address Status # Bytes Next Desc. Ptr. Timestamp CH #9 101 of 203 DS3134 Free Data Buffer (up to 8191 bytes) Free Data Buffer (up to 8191 bytes) First Filled Data Buffer for Channel 2 Single Filled ...
Page 102
... Receive Done Queue Descriptors: Contains Index Pointers to Used Packet Descriptors Up to 64K dwords Done Queue Descriptors Allowed Receive Packet Descriptors: Contains 32-Bit Addresses to Free Buffer as well as Status/Control Information and Links to Other Packet Descriptors Up to 64K Quad dwords Descriptors Allowed 102 of 203 DS3134 ...
Page 103
... Free Descriptor Base + 40h Free Descriptor Base + 50h Channel 2 Second Buffer Descriptor Base + 60h Free Descriptor Base + 70h Channel 2 Last Buffer Descriptor Base + 80h Free Descriptor Base + FFFD0h Free Descriptor Base + FFFF0h Free Descriptor 103 of 203 Address RDBA0 0750h RDBA1 0754h DS3134 ...
Page 104
... Transmit Packet Descriptors have been designed to eliminate the need for the Host to groom the descriptors before transmission. In these types of applications, the Host should not use dword 3 of the Receive Packet Descriptor. Data Buffer Address (32) Next Descriptor Pointer (16) unused (32) 104 of 203 DS3134 HDLC Channel (8) ...
Page 105
... Host and the DMA. On initialization, the Host will configure all of the registers shown in Table 8.1.3B. After initialization, the DMA will only write to (i.e. change) the read pointers and the Host will only write to the write pointers. Free Packet Descriptor Pointer (16) 105 of 203 DS3134 ...
Page 106
... Absolute Address = Free Queue Base + Write Pointer * 8 Absolute Address = Free Queue Base + Read Pointer * 8 Small Absolute Address = Free Queue Base + Small Buffer Start * 8 + Write Pointer * 8 Absolute Address = Free Queue Base + Small Buffer Start * 8 + Read Pointer * 8 < write pointer < write pointer 106 of 203 DS3134 ...
Page 107
... Receive Free Queue End Address Note: Both RFQSBSA & RFQEA are not absolute addresses. i.e. The absolute end address is “Base + RFQEA * 8”. Acronym RFQBA0 RFQBA1 RFQLBWP RFQLBRP RFQSBSA RFQSBWP RFQSBRP RFQEA 107 of 203 DS3134 Address 0700h 0704h 0710h 0718h 070Ch 0714h 071Ch 0708h ...
Page 108
... Host Readied Free Queue Descriptor DMA Acquired Free Queue Descriptor DMA Acquired Free Queue Descriptor DMA Acquired Free Queue Descriptor Host Readied Free Queue Descriptor Host Readied Free Queue Descriptor 108 of 203 DS3134 Large Buffer Circular Queue Small Buffer Circular Queue ...
Page 109
... Free Queue, then it will burst read them, increment the read pointer, and set either the Status Bit for Receive DMA Large Buffer Read (RLBR) or the Status Bit for Receive DMA Small Buffer Read (RSBR) in the Status Register for DMA (SDMA). See Section 4 for more details on Status Bits. 109 of 203 DS3134 ...
Page 110
... V EOF Status (3) BUFCNT(3) Note: 1) Organization of the Done Queue is not affected by the enabling of Big Endian 2) Descriptor Pointer is an index and is not an absolute address RDQFE RFQSF RFQLF n/a n/a RDQT2 HDLC Channel (8) 110 of 203 1 0 n/a RFQFE 9 8 RDQT1 RDQT0 Descriptor Pointer (16) DS3134 ...
Page 111
... If the latter scheme is used, the Host must set this bit to a one when the Done Queue Descriptor is read. The Host will read from the Receive Done Queue to find which data buffers and their associated descriptors are ready for processing. This bit will be set to a zero by the Receive 111 of 203 DS3134 ...
Page 112
... The Receive Done Queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Hence, one descriptor must always remain empty. Receive Done Queue Full State valid descriptor valid descriptor empty descriptor read pointer > valid descriptor valid descriptor valid descriptor valid descriptor < write pointer < write pointer 112 of 203 DS3134 ...
Page 113
... Base + 08h Done Queue Descriptor Host Processed Base + 0Ch Done Queue Descriptor Host Processed Done Queue Descriptor Base + 10h DMA Readied Done Queue Descriptor Base + 14h DMA Readied Done Queue Descriptor 113 of 203 DS3134 Address 0730h 0734h 0740h 073Ch 0738h 0744h ...
Page 114
... Queue FIFO can write descriptors to the Done Queue, then it will burst write them, increment the write pointer, and set the Status Bit for Receive DMA Done Queue Write (RDQW) in the Status Register for DMA (SDMA). See Section 4 for more details on Status bits. 114 of 203 DS3134 ...
Page 115
... Bit 3 / Receive Free Queue Small Buffer FIFO Flush (RFQSF). See Section 8.1.3 for details TC4 TC3 TC2 TC12 TC11 TC10 RDQFE RFQSF RFQLF n/a n/a RDQT2 115 of 203 DS3134 1 0 TC1 TC0 9 8 TC9 TC8 1 0 n/a RFQFE 9 8 RDQT1 RDQT0 ...
Page 116
... Most of the fields within the DMA Configuration RAM are for use by the DMA and the Host will never write to these fields. The Host is only allowed to write (i.e. configure) to the lower word of dword 2 for each HDLC channel. The Host configurable fields are denoted with a thick box as shown below. 116 of 203 DS3134 ...
Page 117
... Current Packet Data Buffer Address (32) Current Descriptor Pointer (16) FBF unused (5) Threshold(3) Offset (4) Fields shown within the thick box are written by the Host; all other fields are for usage by the DMA and can only be read by the Host 117 of 203 DS3134 lsb 0 Size CH (2) EN Size CH (2) ...
Page 118
... Large Buffers when the Buffer Size Select field is set to 10. - FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD - dword 2; Bits Byte Count. The DMA uses these 13 bits to keep track of the number of bytes stored in the data buffer. Maximum is 8191 bytes (0000h =0 bytes / 1FFFh = 8191 bytes). 118 of 203 DS3134 ...
Page 119
... RDMAC register and write it to the channel location indicated by the HCID bits. When the device has completed the write, the IAB bit will be set to zero HCID4 HCID3 HCID2 n/a n/a RDCW2 119 of 203 DS3134 1 0 HCID1 HCID0 9 8 RDCW1 RDCW0 ...
Page 120
... If enabled, the DMA can burst read the Pending Queue Descriptors and burst writes the Done Queue Descriptors. This helps minimize PCI Bus accesses, freeing the PCI Bus more time critical functions. See Sections 8.2.3 and 8.2.4 for more details on this feature D12 D11 D10 120 of 203 DS3134 error occurs in the ...
Page 121
... A dedicated area of memory that the Host will write to inform the DMA that packet data is queued and ready for transmission A dedicated area of memory that the DMA will write to inform the Host that the packet data has been transmitted 121 of 203 DS3134 ...
Page 122
... Note that the packet chain in column 1 was interrupted to transmit the priority packets. In other words, the transmit DMA did not wait for the complete packet to finish transmitting, only the current packet. 122 of 203 DS3134 ...
Page 123
... Next Pend. Desc. EOF = 0 Data Buffer Address EOF CV # Bytes Next Desc. Ptr. unused CH #1 unused PV Next Pend. Desc. 123 of 203 DS3134 Transmitted Data Buffer for Channel 5 1st Transmitted Data Buffer for Channel 1 2nd Transmitted Data Buffer for Channel 1 Last Transmitted Data Buffer ...
Page 124
... Contains Index Pointers to Packet Descriptors of Data Buffers that have been Transmitted Up to 64K dwords Done Queue Descriptors Allowed Transmit Packet Descriptors: Contains 32-Bit Addresses to Data Buffers as well as Status/Control Information and Links to Other Packet Descriptors Up to 64K Quad dwords Descriptors Allowed 124 of 203 DS3134 ...
Page 125
... Packet Descriptor Last Descriptor 1st Descriptor (EOF=1/CV=0) (EOF=0/CV=0) PV=1 Buffer 1 Buffer 1 Packet 3 Packet 5 2nd Descriptor (EOF=0/CV=0) Buffer 2 Packet 3 Last Descriptor (EOF=1/CV=0) Buffer 3 Packet 3 Buffer 1 Packet 4 Packet Chain Column 3 125 of 203 Buffer 1 Packet 6 Buffer 2 Packet 6 Buffer 3 Packet 6 Packet Chain Column 4 dmatpf DS3134 ...
Page 126
... Buffer 1 Pri. Packet 1 Pri. Packet 3 Buffer 2 Pri. Packet 1 Buffer 1 Pri. Packet 2 dmatppf Priority Packet Chain Column 3 126 of 203 1st Descriptor (EOF=0/CV=0) Buffer 1 Pri. Packet 4 2nd Descriptor (EOF=0/CV=0) Buffer 2 Pri. Packet 4 Last Descriptor (EOF=1/CV=0) Buffer 3 Pri. Packet 4 Priority Packet Chain Column 4 DS3134 ...
Page 127
... Channel Reset (CHRST) bit to a one for the next descriptor that it writes to the Pending Queue for the affected channel. As soon as the transmit DMA detects that the CHRST is set to a one, it will re-enable the channel by 127 of 203 DS3134 ...
Page 128
... The transmit DMA constantly reads the Pending Queue looking for packets that are queued for transmission. 2. The transmit DMA will update the Done Queue as packets or data buffers complete transmission error occurs, then the transmit DMA will disable the channel and wait for the Host to request that the channel be enabled. dmaerror 128 of 203 DS3134 ...
Page 129
... Free Descriptor Base + 50h CH 7 2nd Queued Buffer Descriptor Base + 60h Free Descriptor Base + 70h CH 7 Last Queued Buffer Descriptor Base + 80h CH 7 Last Sent Buffer Descriptor Base + FFFD0h Free Descriptor Base + FFFF0h Free Descriptor 129 of 203 DS3134 Address 0850h 0854h ...
Page 130
... Bits Unused. These bits are ignored by the transmit DMA and can be set to any value. Data Buffer Address (32) Next Descriptor Pointer (16) PV Next Pending Descriptor Pointer (16 set to a one when EOF = 1, then this indicates that the Next When set to a one, this bit indicates that the descriptor is the last 130 of 203 DS3134 HDLC Channel (8) ...
Page 131
... DMA. This field will be used when the transmit DMA when it writes to the Done Queue to inform the Host of the status of the outgoing packet data. dword 0; Bits Unused. Not used by the DMA. Can be set to any value by the Host and will be ignored by the transmit DMA. PRI HDLC Channel (8) 131 of 203 Descriptor Pointer (16) DS3134 ...
Page 132
... The Transmit Pending Queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Hence, one descriptor must always remain empty. Transmit Pending Queue Full State valid descriptor valid descriptor empty descriptor read pointer > valid descriptor valid descriptor valid descriptor valid descriptor < write pointer < write pointer 132 of 203 DS3134 ...
Page 133
... DMA Acquired Base + 08h Pending Queue Descriptor DMA Acquired Base + 0Ch Pending Queue Descriptor DMA Acquired Pending Queue Descriptor Base + 10h Host Readied Pending Queue Descriptor Base + 14h Host Readied Pending Queue Descriptor 133 of 203 DS3134 Address 0800h 0804h 080Ch 0810h 0808h ...
Page 134
... Bit 1 / Transmit Pending Queue FIFO Flush (TPQF). When this bit is set to one, the internal Pending Queue FIFO will be flushed (currently loaded Pending Queue Descriptors are lost). This bit must be set to zero for proper operation FIFO in normal operation 1 = FIFO is flushed n/a TDQF TDQFE n/a n/a TDQT2 134 of 203 DS3134 1 0 TPQF TPQFE 9 8 TDQT1 TDQT0 ...
Page 135
... Descriptor Pointer field corresponds to the first descriptor in a HDLC packet (can be a single descriptor) that has been transmitted (DQS = 0) 001 = first buffer transmission complete of a multi (or single) buffer packet (DQS = 1) PRI HDLC Channel (8) 135 of 203 DS3134 Descriptor Pointer (16) ...
Page 136
... The Transmit Done Queue is considered full when the read pointer is ahead of the write pointer by one descriptor. Hence, one descriptor must always remain empty. Transmit Done Queue Full State valid descriptor valid descriptor empty descriptor read pointer > valid descriptor valid descriptor valid descriptor valid descriptor < write pointer < write pointer 136 of 203 DS3134 ...
Page 137
... Base + 08h Done Queue Descriptor Host Processed Base + 0Ch Done Queue Descriptor Host Processed Done Queue Descriptor Base + 10h DMA Readied Done Queue Descriptor Base + 14h DMA Readied Done Queue Descriptor 137 of 203 DS3134 Address 0830h 0834h 0840h 083Ch 0838h 0844h ...
Page 138
... DMA should wait in between writes to the Done Queue. For example, with a PCLK of 33 MHz, the range of wait times are from 7.8 us (RDQFFT = 0001h) to 508 ms (RDQFFT = FFFFh) and PCLK of 25 MHz, the wait times range from 10.2 us (RDQFFT = 0001h) to 671 ms (RDQFFT = FFFFh). 138 of 203 DS3134 ...
Page 139
... Queue FIFO will be flushed by sending all data into the Done Queue. This bit must be set to zero for proper operation FIFO in normal operation 1 = FIFO is flushed TC4 TC3 TC2 TC12 TC11 TC10 n/a TDQF TDQFE n/a n/a TDQT2 139 of 203 DS3134 1 0 TC1 TC0 9 8 TC9 TC8 1 0 TPQF TPQFE 9 8 TDQT1 TDQT0 ...
Page 140
... Next Pending Descriptor Pointer (16) Next Priority Descriptor Pointer (16) Last Priority Pending Descriptor Pointer (16) Fields shown within the thick box are written by the Host; all other fields are for usage by the DMA and can only be read by the Host 140 of 203 DS3134 lsb 0 un- CH DQS used EN ...
Page 141
... FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD - dword 1; Bit 17 / End Of Frame (EOF). This is an internal copy of the EOF field that resides in the current Packet Descriptor that the DMA is operating on. See Section 8.2.2 for more details on the EOF bit. 141 of 203 DS3134 The DMA will ...
Page 142
... Transmit Descriptor Base Address of the first Transmit Packet Descriptor for the packet that is queued up next for transmission. Next Pending Descriptor Pointer field not valid not valid valid valid Next Priority Pending Descriptor Pointer field not valid not valid valid valid 142 of 203 DS3134 ...
Page 143
... Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0. Bits HDLC Channel ID (HCID0 to HCID7). 00000000 (00h) = HDLC Channel Number 1 11111111 (FFh) = HDLC Channel Number 256 HCID4 HCID3 HCID2 n/a TDCW3 TDCW2 143 of 203 DS3134 1 0 HCID1 HCID0 9 8 TDCW1 TDCW0 ...
Page 144
... D15 D14 D13 Note: Bits that are underlined are read only, all other bits are read-write. Bits Transmit DMA Configuration RAM Data (D0 to D15). Data that is written to or read from the Transmit DMA Configuration RAM D12 D11 D10 144 of 203 DS3134 ...
Page 145
... Device ID 0x104 Status 0x108 Class Code 0x10C Header Type 0x110 Base Address for Local Bus 0x13C Vendor ID Command Revision ID Latency Timer Cache Line Size 0x000 Interrupt Pin Interrupt Line Vendor ID Command Revision ID 0x00000 Interrupt Pin Interrupt Line 145 of 203 DS3134 pci_reg ...
Page 146
... They are useful in adapting the PCI bus to a proprietary bus scheme. They are only asserted when the device is a bus master. PCI Bus Read Figure 9.1B PCLK PFRAME* Address PAD CMD Byte Enable #1 PCBE* PIRDY* PTRDY* PDEVSEL* PXAS* PXDS* PXBLAST data #1 data #2 data # 146 of 203 DS3134 9 10 pci_read ...
Page 147
... They are useful in adapting the PCI bus to a proprietary bus scheme. They are only asserted when the device is a bus master. PCI Bus Write Figure 9.1C PCLK PFRAME* Address data #1 PAD CMD BE #1 PCBE* PIRDY* PTRDY* PDEVSEL* PXAS* PXDS* PXBLAST data #2 data # 147 of 203 DS3134 9 10 pci_writ ...
Page 148
... PIDRY* (see Figure 9.1E). If such a scenario occurs, it will be reported via the Master Abort status bit in the PCI Command/Status configuration register (see Section 9.2). PCI Initiator Abort Figure 9.1E PCLK PFRAME* PIRDY* PTRDY* PDEVSEL Bus is Acquired 148 of 203 DS3134 9 10 Bus is Relinquished pci_arb 9 10 pci_iabt ...
Page 149
... This is because the device does not support burst transactions when target. When initiator and experiences a disconnect from the target, it will attempt another bus transaction (if it still has the bus granted) after waiting either one (disconnect without data) or two clock cycles (disconnect with data 149 of 203 DS3134 9 10 pci_tret ...
Page 150
... Figure 9.1J shows an example of a fast back-to-back transaction where no idle cycle exists bus master, Chateau is no capable of performing a Type 2 access target, it can accept both types of fast back-to-back transactions 150 of 203 DS3134 9 10 pci_tdis 9 10 pci_tabt ...
Page 151
... Bits Vendor ID. These read only bits identify Dallas Semiconductor as the manufacturer of the device. The Vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits Device ID. These read only bits identify the DS3134 as the device being used. The Device ID was assigned by Dallas Semiconductor and is fixed at 3134h. ...
Page 152
... Bit 4 / Memory Write & Invalidate Command Enable (MWEN). This read only bit is forced to zero by the device to indicate that it cannot generate the Memory Write and Invalidate command. MWEN SCC MASC Reserved (Read Only / set to all zeros) TABTM TABT DTS1 152 of 203 DS3134 lsb MSC IOC FBBEN PSEC DTS0 PARR ...
Page 153
... Bit 24 / PCI Parity Error Reported (PARR). This read/write bit will be set to a one when the device is a bus master and detects or asserts the PPERR* signal when the PARC command bit is enabled. This bit can be reset (set to zero) by the Host by writing a one to this bit parity errors have been detected 1 = parity errors detected 153 of 203 DS3134 ...
Page 154
... See Appendix D of PCI Local Bus Specification Revision 2.1 for details. Bits Class Code Sub-Class. These read only bits identify the sub-class value for the device and are fixed at 80h, which indicate "Other Network Controller". See Appendix D of PCI Local Bus Specification Revision 2.1 for details. 154 of 203 DS3134 lsb ...
Page 155
... Register Description: PCI Device Configuration Memory Base Address Register Register Address: 0x010h Base Address (Read Only / set to 0h) Base Address msb Cache Line Size Latency Timer PF TYPE1 Base Address (Read Only / set to 0h) Base Address Base Address 155 of 203 DS3134 lsb lsb TYPE0 MSI ...
Page 156
... Bits Maximum Latency. These read only bits are used to indicate to the Host, how often the device needs to gain access to the PCI bus. The value placed in these bits specifies a period of time in 0.25 us increments. These bits are forced to 0Fh. Interrupt Line 156 of 203 DS3134 lsb ...
Page 157
... Bits Vendor ID. These read only bits identify Dallas Semiconductor as the manufacturer of the device. The Vendor ID was assigned by the PCI Special Interest Group and is fixed at 13EAh. Bits Device ID. These read only bits identify the DS3134 as the device being used. The Device ID was assigned by Dallas Semiconductor and is fixed at 3134h. ...
Page 158
... PSERR* pin Bit 9 / Fast Back-to-Back Master Enable (FBBEN). This read only bit is forced to zero by the device to indicate that it is not capable of generating fast back-to-back transactions to different agents. Bits Reserved. These read only bits are forced to zero by the device. 158 of 203 DS3134 ...
Page 159
... Bit 31 / PCI Parity Error Reported (PPE). This read/write bit will be set to a one when the device detects a parity error (even if parity is disabled via the PARC Command bit). This bit can be reset (set to zero) by the Host by writing a one to this bit. 159 of 203 DS3134 ...
Page 160
... Bits Latency Timer. These read only bits are forced to a zero by the device since the device cannot act as a bus master. Bits Header Type. These read only bits are forced to 80h, which indicate a multifunction device. Bits Built-In Self Test (BIST). These read only bits are forced to zero. 160 of 203 DS3134 lsb lsb ...
Page 161
... Bits Base Address. These read/write bits define the location of the 1M byte memory space that is mapped to the Local Bus. These bits correspond to the most significant bits of the PCI address space. PF TYPE1 Base Address (Read Only / set to 0h) Base Address Base Address 161 of 203 DS3134 lsb TYPE0 MSI ...
Page 162
... Bits Interrupt Pin. These read only bits are forced to 01h to indicate that the uses PINTA interrupt. Bits Minimum Grant. These read only bits are forced to zero. Bits Maximum Latency. These read only bits are forced to zero. Interrupt Line 162 of 203 DS3134 lsb ...
Page 163
... Figure 10.1C displays an example of the Configuration Mode. In this mode, the CPU on the Local Bus will configure and monitor the DS3134. In this mode, the Host on the PCI/Custom Bus cannot access the DS3134 and the PCI/Custom Bus is only used to transfer HDLC packet data to and from the Host. ...
Page 164
... Bridge Mode Figure 10. DS3134 Chateau Framer or Transceiver Framer or Transceiver Framer or Transceiver Framer or Transceiver Local Bus Bridge Mode with Arbitration Enabled Figure 10. Framer or Transceiver Framer or Transceiver Framer or Transceiver Framer or Transceiver Local Bus Local CPU that Handles the Real Time Tasks Required by the Interfaces ...
Page 165
... Transceiver Local Bus CPU Confgures and Monitors DS3134 PCI Bridge Mode In the PCI Bridge Mode, data from the PCI bus can be transferred to the Local Bus. In this mode, the Local Bus acts as a "master" and can create all the needed signals to control the bus. In the PCI Bridge Mode, the user must configure the Local Bus Bridge Mode Control Register (LBBMC) which is described in Section 10 ...
Page 166
... The 16-bit data picked from the PCI bus will be routed/sample to/from the LD[7:0] & LD[15:8] signal lines as shown PCBE* signals are asserted during an access, a Target Abort is not return and no transaction occurs on the Local Bus. LBHE LD[15:8] LD[7:0] 0 active 1 active 0 active active 0 active 1 active 0 active active 166 of 203 DS3134 LBHE ...
Page 167
... In the Configuration Mode, all bus accesses are based on 16-bit addresses and 16-bit data. The upper four addresses (LA[19:16]) are ignored and 8-bit data accesses are not allowed. See Section 12 for details on the AC timing requirements. 167 of 203 DS3134 ...
Page 168
... Local Bus? Yes Is the Local Bus Granted? No Yes Are there 16 Clocks No Remaining? Yes Is the External Local Bus Ready (LRDY*) Being Used? No Local Bus Access Progresses Normal Access PCI Target Retry Occurs 168 of 203 Request the Bus lb_fc1 Issued DS3134 ...
Page 169
... LCLK periods 1000 = bus transaction is defined as 8 LCLK periods 1001 = bus transaction is defined as 9 LCLK periods 1010 = bus transaction is defined as 10 LCLK periods LRDY2 LRDY1 LRDY0 n/a LAT3 LAT2 169 of 203 DS3134 1 0 LARBE LCLKE 9 8 LAT1 LAT0 ...
Page 170
... LCLKs 1110 = when granted, hold the bus for 524288 LCLKs 1111 = when granted, hold the bus for 1048576 LCLKs 33 MHz 0.97 us 1.9 us 3.9 us 7.8 us 15.5 us 7.9 ms 15.9 ms 31.8 ms 170 of 203 DS3134 25 MHz 1.3 us 2.6 us 5.1 us 10.2 us 20.5 us 10.5 ms 21.0 ms 41.9 ms ...
Page 171
... If the bus has already been granted (LBGACK* asserted), then the timing shown at the bottom of the page will occur. LCLK LHOLD LHLDA LBGACK* Note LBHE* / LWR* / LRD* are tri-stated. LCLK tri-state LA[19:0] LD[7:0] LD[15:8] tri-state LBHE* tri-state LWR* tri-state LRD 1048576 LCLKs Address Valid 171 of 203 DS3134 lb pi ...
Page 172
... LCLK LHOLD LHLDA LBGACK* Note LBHE* / LWR* / LRD* are tri-stated. LCLK tri-state LA[19:0] tri-state LD[7:0] tri-state LD[15:8] tri-state LBHE* tri-state LRD* tri-state LWR 1048576 LCLKs Address Valid Data Valid Data Valid 172 of 203 DS3134 lb_pi ...
Page 173
... LCLK LA[19:0] LD[7:0] LD[15:8] LBHE* LWR* LRD* LRDY* Note: The LRDY* signal must be detected by the 9th LCLK or the bus access attempted by the Host will be unsuccessful and the LBE status bit will be set Address Valid 173 of 203 DS3134 lb_pi1_V2 10.3C 03/22/99 ...
Page 174
... LA[19:0] LD[7:0] LD[15:8] LBHE* LRD* LWR* LRDY* Note: The LRDY* signal must be detected by the 9th LCLK or the bus access attempted by the Host will be unsuccessful and the LBE status bit will be set Address Valid Data Valid 174 of 203 DS3134 lb_pi1_v2 10.3D 03/22/99 ...
Page 175
... If the bus has already been granted (LBGACK* asserted), then the timing shown at the bottom of the page will occur. LCLK LBR* LBG* LBGACK* Note LBHE* / LDS* / LR/W* are tri-stated. LCLK tri-state LA[19:0] LD[7:0] LD[15:8] tri-state LBHE* tri-state LR/W* tri-state LDS 1048576 LCLKs Address Valid Data Valid 175 of 203 DS3134 6 lb_pm ...
Page 176
... If the bus has already been granted (LBGACK* asserted), then the timing shown at the bottom of the page will occur. LCLK LBR* LBG* LBGACK* Note LBHE* / LDS* / LR/W* are tri-stated. LCLK tri-state LA[19:0] tri-state LD[7:0] LD[15:8] tri-state LBHE* tri-state LR/W* tri-state LDS 1048576 LCLKs Address Valid Data Valid tri-state 176 of 203 DS3134 6 lb_pm ...
Page 177
... LCLK 1 2 LA[19:0] LD[7:0] LD[15:8] LBHE* LR/W* LDS* LRDY* Note: The LRDY* signal must be detected by the 9th LCLK or the bus access attempted by the Host will be unsuccessful and the LBE status bit will be set Address Valid 177 of 203 DS3134 lb_pm1_v2 10.3G 03/22/99 ...
Page 178
... LD[7:0] LD[15:8] LBHE* LR/W* LDS* LRDY* Note: The LRDY* signal must be detected by the 9th LCLK or the bus access attempted by the Host will be unsuccessful and the LBE status bit will be set Address Valid Data Valid tri-state 178 of 203 DS3134 lb_pm1_v2 10.3H\ 03/22/99 ...
Page 179
... The DS3134 device supports the standard instruction codes SAMPLE/PRELOAD, BYPASS, and EXTEST. Optional public instructions included are HIGHZ, CLAMP, and IDCODE. See Figure 11.1A for a Block Diagram. The DS3134 contains the following items, which meet the requirements, set by the IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture: ...
Page 180
... Test-Logic-Reset Upon power-up of the DS3134, the TAP controller will be in the Test-Logic-Reset state. The Instruction register will contain the IDCODE instruction. All system logic on the DS3134 will operate normally. Run-Test-Idle Run-Test-Idle is used between scan operations or during specific tests. The Instruction register and Test register will remain idle ...
Page 181
... The Capture-IR state is used to load the shift register in the Instruction register with a fixed value. This value is loaded on the rising edge of JTCLK. If JTMS is high on the rising edge of JTCLK, the controller will enter the Exit1-IR state. If JTMS is low on the rising edge of JTCLK, the controller will enter the Shift-IR state. 181 of 203 DS3134 ...
Page 182
... JTMS high will move the controller to the Update-IR state. The falling edge of that same JTCLK will latch the data in the instruction shift register to the instruction parallel output. Instructions supported by the DS3134 and their respective operational binary codes are shown in Table 11.3A. Instruction Codes Table 11.3A ...
Page 183
... The device ID code will always have a one in the LSB position. The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed by 16 bits for the device and 4 bits for the version. The device ID code for the DS3134 is 00006143h. 11.4 TEST REGISTERS IEEE 1149.1 requires a minimum of two Test registers ...
Page 184
... I/O I/O I/O I/O I/O I/O I/O I/O I LINT input LINT output I LWR input LWR output I LRD input LRD output I LA0 to LA19 are inputs; LA0 to LA19 are outputs I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O 184 of 203 DS3134 ...
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... RC12 A10 135 RS12 B10 134 RD12 C10 133 TC12 A9 132 TS12 B9 131 TD12 C9 130 RC13 B8 129 RS13 C8 128 RD13 A7 127 TC13 B7 126 TS13 A6 I/O Control Bit Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I 185 of 203 DS3134 ...
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... G3 97 TC2 G2 96 TS2 G1 95 TD2 H3 94 RC3 H2 93 RS3 H1 92 RD3 J4 91 TC3 J3 90 TS3 J2 89 TD3 J1 88 RC4 M1 87 RS4 M2 86 RD4 M3 85 TC4 N1 84 TS4 N2 83 TD4 N3 82 RC5 P1 81 RS5 P2 I/O Control Bit Description 186 of 203 DS3134 ...
Page 187
... I/O Control Bit Description PAD0 to PAD31 are inputs;PAD0 to PAD31 are outputs I/O I/O I/O I/O I/O I/O I/O I PCBE3 input PCBE3 output I I/O I/O I/O I/O I/O I/O I/O I PCBE2 input PCBE2 output I PFRAME input PFRAME output I/O 187 of 203 DS3134 ...
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... PSTOP input PSTOP output I PPERR input PPERR output I PPAR is an input PPAR is an output I PCBE1 input PCBE1 output I/O I/O I/O I/O I/O I/O I/O I/O I PCBE0 input PCBE0 output I/O I/O I/O I/O I/O I/O I/O I/O I 188 of 203 DS3134 ...
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... VIL -0.3 VILS -0 +70 C; VDD = 3.0V TO 3.6V) Symbol Min Typ IDD CIO 7 VTH 0.6 IIL -10 IILP -500 ILO -10 IOH -4.0 IOL +4.0 189 of 203 DS3134 ( +70 C) Max Units Notes 5.5 V 5.5 V 0.8 V 0.7 V 3.6 V Max Units Notes TBD + +500 ...
Page 190
... Hold Time from the Falling Edge or Rising Edge Delay from the Rising Edge or Falling Edge Data Valid on TD Notes: 1. Ports applications running MHz. 2. Port 0 or Port 1 running in applications MHz +70 C; VDD = 3.0V TO 3.6V) Symbol Min Typ t1 100 190 of 203 DS3134 Max Units Notes – – ...
Page 191
... LD[15:0] Set Up Time to the Rising Edge of LCLK LD[15:0] Hold Time from the Rising Edge of LCLK Input Set Up Time to the Rising Edge of LCLK Input Hold Time from the Rising Edge of LCLK +70 C; VDD = 3.0V TO 3.6V) Symbol Min 191 of 203 Typ Max Units DS3134 Notes ...
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... LOCAL BUS BRIDGE MODE (LMS = 0) AC TIMING DIAGRAM Figure 12B LCLK LA[19:0] / LD[15:0] / LBHE* / LWR*(LR/W*) / LRD*(DS) LA[19:0] / LWR*(LR/W*) / LRD*(LDS*) / LBHE* LA[19:0] / LWR*(LR/W*) / LRD*(DS) / LHOLD(LBR*) / LBGACK* LD[15:0] LINT* / LRDY* LHLDA(LBG*) t1 Tri-State Data Valid 192 of 203 Data Valid t2 Tri-State Data Valid lbus_ac DS3134 ...
Page 193
... Wait Time from Either LWR* or LDS* Active to Latch LD[15:0] LD[15:0] Set Up Time to Either LWR* or LDS* Inactive LD[15:0] Hold Time from Either LWR* or LDS* Inactive LA[15:0] Hold from Either LWR* or LDS* Inactive ( +70 C; VDD = 3.0V TO 3.6V) Symbol Min Typ 193 of 203 DS3134 Max Units Notes ns ns 120 ...
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... LOCAL BUS CONFIGURATION MODE (LMS = 1) AC TIMING DIAGRAM Figure 12C Intel Read Cycle LA[15:0] Address Valid LD[15:0] LWR* t1 LCS* LRD* LOCAL BUS CONFIGURATION MODE (LMS = 1) AC TIMING DIAGRAM Figure 12C Continued Intel Write Cycle LA[15:0] Address Valid LD[15:0] LRD* t1 LCS* LWR* Data Valid 194 of 203 lb_ac1 DS3134 ...
Page 195
... Motorola Read Cycle LA[15:0] Address Valid LD[15:0] LR/W* t1 LCS* LDS* Motorola Write Cycle LA[15:0] Address Valid LD[15:0] LR/W* t1 LCS* LDS* Data Valid 195 of 203 lb_ac1 DS3134 ...
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... PCI BUS INTERFACE AC TIMING DIAGRAM Figure 12D PCLK PCI Input & I/O PCI Output & I/O PCI Output & I/O to Tri-State PCI Output & Tri-State I/O from Tri-State ( +70 C; VDD = 3.0V TO 3.6V) Symbol Min Data Valid t8 196 of 203 Typ Max Units Tri-State Data Valid pci_ac DS3134 Notes ...
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... Rising Edge of JTCLK Delay Time from the Falling Edge of JTCLK to Data Valid on JTDO JTAG TEST PORT INTERFACE AC TIMING DIAGRAM Figure 12E t2 JTCLK JTMS / JTDI t6 JTDO ( +70 C; VDD = 3.0V TO 3.6V) Symbol Min Typ t1 1000 t2 400 t3 400 197 of 203 DS3134 Max Units Notes jtag_ac ...
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... SECTION 13: MECHANICAL DIMENSIONS 198 of 203 DS3134 ...
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... The T1 and E1 channelized application examples shown in Section 14 will be one of two types. The first type is where a single data stream is routed to and from the DS3134. This first type is represented as a thin arrow in the application examples and the electrical connections are shown in Figure 14B. The second type is where four data streams have been Time Division Multiplexed (TDM) into a single 8 ...
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... QUAD T1/E1 CONNECTION Figure 14C 16 Port with 256 HDLC Channel Support Figure 14D shows an application where 16 T1 ports are interfaced to a single DS3134. application, the T1 lines can be either clear channel or channelized. The DS21Q552 Quad T1 Transceiver performs the line interface function and frames to the T1 line. To convert this application design, the DS21Q552 is replaced with the DS21Q554 Quad E1 Transceiver, which is pin-for-pin compatible ...