DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 131

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.2.3 PENDING QUEUE
The Host will write to the Transmit Pending Queue, the location of the readied descriptor, channel
number and control information. The descriptor space is indicated via a 16-bit pointer which the DMA
will use along with the Transmit Packet Descriptor Base Address to find the exact 32-bit address of the
associated Transmit Packet Descriptor.
Transmit Pending Queue Descriptor Figure 8.2.3A
dword 0
Note:
1) rganization of the Pending Queue is not affected by the enabling of Big Endian
2) Descriptor pointer is an index and not an absolute address.
dword 0; Bits 0 to 15 / Descriptor Pointer. This 16-bit value is the offset from the Transmit Descriptor
Base Address to the first descriptor in a packet chain (can be a single descriptor) that is queued up for
transmission.
dword 0; Bits 16 to 23 / HDLC Channel Number. HDLC channel number, which can be from 1 to
256.
dword 0; Bit 24 / Priority Packet (PRI). If this bit is set to a one, then this indicates to the transmit
DMA that the packet or packet chain pointed to by the Descriptor Pointer field should be transmitted
immediately after the current packet transmission (whether it be standard or priority) is complete.
dword 0; Bit 25 / Channel Reset (CHRST). Under normal operating conditions, this bit should always
be set to zero. When an error condition occurs and the transmit DMA places the channel into an out-of-
service state by setting the Channel Enable (CHEN) bit in the Transmit DMA Configuration Register to
zero, the Host can force the channel active again by setting the CHRST bit to a one. Only the first
descriptor loaded into the Pending Queue after an error condition should have CHRST set to a one, all
subsequent descriptors (until another error condition occurs) should have CHRST set to zero. The
transmit DMA examines this bit and will force channel active (CHEN = 1) if CHRST is set to one. If
CHRST is set to zero, then the transmit DMA will not modify the state of the CHEN bit. See Section
8.2.1 for more details on how error conditions are handled.
dword 0; Bits 26 to 28 / Packet Status. Not used by the DMA. Can be set to any value by the Host and
will be ignored by the transmit DMA. This field will be used when the transmit DMA when it writes to
the Done Queue to inform the Host of the status of the outgoing packet data.
dword 0; Bits 29 to 31 / Unused. Not used by the DMA. Can be set to any value by the Host and will
be ignored by the transmit DMA.
unused
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
Status(3)
CH RST
PRI
HDLC Channel (8)
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Descriptor Pointer (16)
DS3134