DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 183

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS3134
SAMPLE/PRELOAD
A mandatory instruction for the IEEE 1149.1 specification. This instruction supports two functions. The
digital I/Os of the DS3134 can be sampled at the Boundary Scan register without interfering with the
normal operation of the device by using the Capture-DR state. SAMPLE/PRELOAD also allows the
DS3134 to shift data into the Boundary Scan register via JTDI using the Shift-DR state.
EXTEST
EXTEST allows testing of all interconnections to the DS3134. When the EXTEST instruction is latched
in the instruction register, the following actions occur. Once enabled via the Update-IR state, the parallel
outputs of all digital output pins will be driven. The Boundary Scan register will be connected between
JTDI and JTDO. The Capture-DR will sample digital inputs into the Boundary Scan register.
BYPASS
When the BYPASS instruction is latched into the parallel Instruction register, JTDI connects to JTDO
through the one-bit Bypass Test register. This allows data to pass from JTDI to JTDO not affecting the
device's normal operation.
IDCODE
When the IDCODE instruction is latched into the parallel Instruction register, the Identification Test
register is selected. The device identification code will be loaded into the Identification register on the
rising edge of JTCLK following entry into the Capture-DR state. Shift-DR can be used to shift the
identification code out serially via JTDO. During Test-Logic-Reset, the identification code is forced into
the instruction register's parallel output. The device ID code will always have a one in the LSB position.
The next 11 bits identify the manufacturer's JEDEC number and number of continuation bytes followed
by 16 bits for the device and 4 bits for the version. The device ID code for the DS3134 is 00006143h.
11.4 TEST REGISTERS
IEEE 1149.1 requires a minimum of two Test registers; the Bypass register and the Boundary Scan
register. An optional Test register has been included in the DS3134 design. This Test register is the
Identification register and is used in conjunction with the IDCODE instruction and the Test-Logic-Reset
state of the TAP controller.
Bypass Register
This is a single one-bit shift register used in conjunction with the BYPASS, CLAMP, and HIGHZ
instructions, which provides a short path between JTDI and JTDO.
Identification Register
The Identification register contains a 32-bit shift register and a 32-bit latched parallel output. This
register is selected during the IDCODE instruction and when the TAP controller is in the Test-Logic-
Reset state.
Boundary Scan Register
This register contains both a shift register path and a latched parallel output for all control cells and digital
I/O cells and is TBD bits in length. Table 11.4A shows all of the cell bit locations and definitions.
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