DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 148

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PCI Bus Arbitration
The PCI bus can be arbitrated as shown in Figure 9.1D. The initiator will request bus access by asserting
PREQ*. A central arbiter will grant the access some time later by asserting PGNT*. Once the bus has
been granted, the initiator will wait until both PIRDY* and PFRAME* are deasserted (i.e. an idle cycle)
before acquiring the bus and beginning the transaction. As shown in Figure 9.1C, the bus was still being
used when it was granted and the device had to wait until clock cycle #6 before it acquired the bus and
begin the transaction. The arbiter can deassert PGNT* at any time and the initiator must relinquish the
bus after the current transfer is complete (which can be limited by the latency timer).
PCI Bus Arbitration Signaling Protocol Figure 9.1D
PCLK
PREQ*
PGNT*
PFRAME*
PCI Initiator Abort
If a target fails to respond to an initiator by asserting PDEVSEL* and PTRDY* within 5 clock cycles,
then the initiator will abort the transaction by deasserting PFRAME* and then one clock later deasserting
PIDRY* (see Figure 9.1E). If such a scenario occurs, it will be reported via the Master Abort status bit in
the PCI Command/Status configuration register (see Section 9.2).
PCI Initiator Abort Figure 9.1E
PCLK
PFRAME*
PIRDY*
PTRDY*
PDEVSEL*
1
1
Wait for PGNT* Asserted
and then PFRAME* &
PIRDY* Deasserted
2
2
3
3
4
4
5
5
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6
6
Bus is Acquired
7
7
8
8
9
9
Bus is
Relinquished
pci_arb
pci_iabt
10
10
DS3134