DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 11

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DS3134
In the receive path, the following process occurs. The HDLC Engines collect the incoming data into
32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are
priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the
FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC
channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has no
bearing on the priority of this data transfer. This situation is of no real concern however since the
DS3134 has been designed to handle up to 104 Mbps in both the receive and transmit directions without
any potential loss of data due to priority conflicts in the transfer of data from the HDLC Engines to the
FIFO and vice versa.
The FIFO transfers data from the HDLC Engines into the FIFO and checks to see if the FIFO has filled to
beyond the programmable High Water Mark. If it has, then the FIFO signals to the DMA that data is
ready to be burst read from the FIFO to the PCI Bus. The FIFO Block controls the DMA Block and it
tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS3134 can handle
multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need to
have data transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the
DMA will handle next via a Host configurable algorithm, which allows the selection to be either round
robin or priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the
application, the selection of this algorithm can be quite important. The DS3134 cannot control when it
will be granted PCI Bus access and if bus access is restricted, then the Host may wish to prioritize which
HDLC channels get top priority access to the PCI Bus when it is granted to the DS3134.
When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO
(even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC
packet is not large enough to fill the FIFO to the High Water Mark, then the FIFO will not wait for more
data to enter the FIFO, it will signal the DMA that a End Of Frame (EOF) was detected and that data is
ready to be transferred from the FIFO to the PCI Bus by the DMA.
In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC
(Layer 2) Engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority
decoded with Port 0 getting the highest priority. Hence, if multiple ports are requesting packet data, the
FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports
before moving on to the higher numbered ports. Again there is no potential loss of data as long as the
transmit throughput maximum of 104 Mbps is not exceeded. When the FIFO detects that a HDLC Engine
needs data, it then transfers the data from the FIFO to the HDLC Engines in 8-bit chunks. If the FIFO
detects that the FIFO is below the Low Water Mark, it then checks with the DMA to see if there is any
data available for that HDLC Channel. The DMA will know if any data is available because the Host on
the PCI Bus will have informed it of such via the Pending Queue Descriptor. When the DMA detects that
data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest
priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS3134 can handle
multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need the
DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the
DMA will handle next via a Host configurable algorithm, which allows the selection to be either round
robin or priority, decoded (with HDLC Channel 1 getting the highest priority).
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