DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 141

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

dword 0; Bits 0 to 31 / Current Data Buffer Address. The current 32-bit address of the data buffer that
is being used. This address is used by the DMA to keep track of where data should be read from as it is
passed to the transmit FIFO.
- HOST MUST CONFIGURE -
dword 1; Bit 0 / Channel Enable (CHEN). This bit is controlled by both the Host and the transmit
DMA to enable and disable a HDLC channel. The DMA will automatically disable a channel when an
error condition occurs (see Section 8.2.1 for a discussion on error conditions).
automatically enable a channel when it detects that the Channel Reset (CHRST) bit in the Pending Queue
descriptor is set to a one.
- HOST MUST CONFIGURE -
dword 1; Bit 1 / Done Queue Select (DQS). This bit determines whether the transmit DMA will write
to the Done Queue only after a complete HDLC packet (which may be only a single buffer) has been
transmitted (in which case the Descriptor Pointer in the Done Queue will correspond to the first descriptor
of the packet) or whether it should write to the Done Queue after each data buffer has been transmitted (in
which case the Descriptor Pointer in the Done Queue will correspond to a single data buffer). The setting
of this bit also affects the reporting of the Status field in the Transmit Done Queue. When DQS = 0, the
only non-errored status possible is a setting of 000. When DQS = 1, then the non-errored settings of 001,
010, and 011 are possible.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 1; Bit 2/ Unused. This field is not used by the DMA and could be any value when read.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 1; Bits 3 to 15 / Byte Count. The DMA uses these 13 bits to keep track of the number of bytes
stored in the data buffer. Maximum is 8191 bytes (0000h =0 bytes / 1FFFh = 8191 bytes).
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 1; Bit 16 / Chain Valid (CV). This is an internal copy of the CV field that resides in the current
Packet Descriptor that the DMA is operating on. See Section 8.2.2 for more details on the CV bit.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
dword 1; Bit 17 / End Of Frame (EOF). This is an internal copy of the EOF field that resides in the
current Packet Descriptor that the DMA is operating on. See Section 8.2.2 for more details on the EOF
bit.
- FOR DMA USAGE ONLY / HOST CAN ONLY READ THIS FIELD -
0 = HDLC Channel Disabled
1 = HDLC Channel Enabled
0 = write to the Done Queue only after a complete HDLC packet has been transmitted
1 = write to the Done Queue after each data buffer is transmitted
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The DMA will
DS3134