DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 150

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PCI Target Disconnect Figure 9.1G
PCLK
PFRAME*
PSTOP*
PDEVSEL*
PCI Target Abort
Targets can also abort the current transaction which means that it does not wish for the initiator to attempt
the request again. No data is transferred in a target abort scenario. A target abort is signaled to the
initiator by the simultaneous assertion of PSTOP* and deassertion of PDEVSEL* (see Figure 9.1H).
When Chateau is a target, it will only issue a target abort when the Host is accessing the Local Bus. This
will occur when the Host attempts a bus transaction with a combination of bytes enables (PCBE*) that is
not supported by the Local Bus. If such a scenario occurs, it will be reported via the Target Abort
Initiated status bit in the PCI Command/Status configuration register (see Section 9.2). See Section 10.1
for details on Local Bus operation. When Chateau is a bus master, if it detects a target abort, then it will
be reported via the Target Abort Detected by Master status bit in the PCI Command/Status configuration
register (see Section 9.2).
PCI Target Abort Figure 9.1H
PCLK
PFRAME*
PTRDY*
PSTOP*
PDEVSEL*
PCI Fast Back-to-Back
Fast back-to-back transactions are two consecutive bus transactions without the usually required idle
cycle (PFRAME* and PIRDY* deasserted) between them. This can only occur when there is a guarantee
that there will not be any contention on the signal lines. The PCI specification allows two types of fast
back-to-back transactions, those that access the same agent (Type 1) and those that do not (Type 2).
Figure 9.1J shows an example of a fast back-to-back transaction where no idle cycle exists. As a bus
master, Chateau is no capable of performing a Type 2 access. As a target, it can accept both types of fast
back-to-back transactions.
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