DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 63

IC CTRLR HDLC CHATEAU 256-BGA

DS3134

Manufacturer Part Number
DS3134
Description
IC CTRLR HDLC CHATEAU 256-BGA
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of DS3134

Controller Type
HDLC Controller
Interface
Serial
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
500mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
256-BGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant

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Register Name:
Register Description: Channelized Layer 1 DS0 Data Register
Register Address:
Note: Bits that are underlined are read only, all other bits are read-write.
Note: In normal device operation, the Host must never write to the C[n]DAT[j] registers.
Bits 0 to 7 / Receive DS0 Data (RDATA). This register holds the most current DS0 byte received. It is
used by the transmit side Layer One State Machine when Channelized Network LoopBack (CNLB) is
enabled.
Bits 8 to 15 / Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted.
It is used by the receive side Layer One State Machine when Channelized Local LoopBack (CLLB) is
enabled.
Register Name:
Register Description: Receive Layer 1 Configuration Register
Register Address:
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 7 / Receive Channel Number (RCH#). The CPU will load the number of the HDLC channel
associated with this particular DS0 channel. If the port is running in an unchannelized mode (RUEN = 1),
then the HDLC Channel Number only needs to be loaded into R[n]CFG0. If the Fast (52 Mbps) HDLC
Engine is enabled on Port 0, then HDLC Channel 1 is assigned to it and likewise HDLC Channel 2 will
be assigned to the Fast HDLC Engine on Port 2 if it is enabled. Hence, these HDLC channel numbers
should not be used if the Fast HDLC Engines are enabled.
RCHEN
15
15
7
7
00000000 (00h) = HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0)
00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1)
00000010 (02h) = HDLC Channel Number 3
11111111 (FFh) = HDLC Channel Number 256
RBERT
14
14
6
6
C[n]DAT[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0
Indirect Access Via CP[n]RD
R[n]CFG[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0
Indirect Access via CP[n]RD
RCH#(8): Receive HDLC Channel Number
n/a
13
13
5
5
TDATA(8): Transmit DS0 Data
RDATA(8): Receive DS0 Data
RV54
12
12
4
4
63 of 203
n/a
11
11
3
3
CLLB
10
10
2
2
n/a
1
9
1
9
R56
0
8
0
8
DS3134

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