DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 72

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Register Name:
Register Description: BERT Control Register 0
Register Address:
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Force Resynchronization (RESYNC).
synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high
whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for
a subsequent resynchronization. Note: Bit 2, 3 & 4 must be set, minimum of 64 system clock cycles,
before toggle the Resync bit (bit 0).
Bit 1 / Load Bit and Error Counters (LC). A low to high transition latches the current bit and error
counts into the host accessible registers BERTBC and BERTEC and clears the internal count. This bit
should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be
cleared and set again for a subsequent loads.
Bit 2 / Pattern Select Bit 0 (PS0).
Bit 3 / Pattern Select Bit 0 (PS1).
Bit 4 / Pattern Select Bit 1 (PS2).
Bit 5 / Receive Invert Data Enable (RINV).
Bit 6 / Transmit Invert Data Enable (TINV).
Bit 8 / Repetitive Pattern Length Bit 0 (RPL0).
Bit 9 / Repetitive Pattern Length Bit 1 (RPL1).
Bit 10 / Repetitive Pattern Length Bit 2 (RPL2).
IESYNC
n/a
15
7
000 = Pseudorandom Pattern 2E7 - 1
001 = Pseudorandom Pattern 2E11 - 1
010 = Pseudorandom Pattern 2E15 - 1
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = illegal state
111 = illegal state
0 = do not invert the incoming data stream
1 = invert the incoming data stream
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
IEBED
TINV
14
6
BERTC0
0500h
RINV
IEOF
13
5
PS2
n/a
12
4
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RPL3
PS1
11
3
A low to high transition will force the receive BERT
RPL2
PS0
10
2
RPL1
LC
1
9
RESYNC
RPL0
0
8
DS3134