DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 133

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Transmit Pending Queue Internal Address Storage Table 8.2.3A
Register Name
Transmit Pending Queue Base Address 0 (lower word)
Transmit Pending Queue Base Address 1 (upper word)
Transmit Pending Queue Host Write Pointer
Transmit Pending Queue DMA Read Pointer
Transmit Pending Queue End Address
Note: Transmit Free Queue End Address is not an absolute address. The absolute end address is “Base +
TPQEA”.
Transmit Pending Queue Structure Figure 8.2.3B
Pending Queue Host Write Pointer
Pending Queue DMA Read Pointer
Maximum of 65536
Pending Queue Descriptors
Once the Transmit DMA is activated (by setting the TDE control bit in the Master Configuration register;
see Section 4), it can begin reading data out of the pending queue. It knows where to read data out of the
pending queue by reading the Read Pointer and adding it to the Base Address to obtain the actual 32-bit
address. Once the DMA has read the Pending Queue, it increments the Read Pointer by one dword. A
check must be made to make sure the incremented address does not exceed the Transmit Pending Queue
End Address. If the incremented address does exceed this address, then the incremented read pointer will
be set equal to 0000h.
Status / Interrupts
On each read of the Pending Queue by the DMA, the DMA will set the Status Bit for Transmit DMA
Pending Queue Read (TPQR) in the Status Register for DMA (SDMA). The status bits can also (if
enabled) cause a hardware interrupt to occur. See Section 4 for more details.
dmatpq
Base + End Address
Base + 00h
Base + 04h
Base + 08h
Base + 0Ch
Base + 10h
Base + 14h
133 of 203
Pending Queue Descriptor
Pending Queue Descriptor
Pending Queue Descriptor
Pending Queue Descriptor
Pending Queue Descriptor
Pending Queue Descriptor
Pending Queue Descriptor
DMA Acquired
DMA Acquired
DMA Acquired
Host Readied
Host Readied
Host Readied
Host Readied
Acronym
TPQBA0
TPQBA1
TPQWP
TPQRP
TPQEA
Address
080Ch
0800h
0804h
0810h
0808h
DS3134