DS3134 Maxim Integrated Products, DS3134 Datasheet - Page 137

• Manufacturer Part Number: DS3134
• Description: IC CTRLR HDLC CHATEAU 256-BGA
• Manufacturer: Maxim Integrated Products

Specifications of DS3134

• Controller Type: HDLC Controller
• Interface: Serial
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 500mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Transmit Done Queue Internal Address Storage Table 8.2.4A
Register Name
Transmit Done Queue Base Address 0 (lower word)
Transmit Done Queue Base Address 1 (upper word)
Transmit Done Queue DMA Write Pointer
Transmit Done Queue Host Read Pointer
Transmit Done Queue End Address
Transmit Done Queue FIFO Flush Timer
Note: Transmit Done Queue End Address is not an absolute address. The absolute end address is “Base +
TDQEA * 4”.
Transmit Done Queue Structure Figure 8.2.4B
Once the Transmit DMA is activated (via the TDE control bit in the Master Configuration register; see
Section 4 for more details), it can begin writing data to the Done Queue. It knows where to write data
into the Done Queue by reading the Write Pointer and adding it to the Base Address to obtain the actual
32-bit address. Once the DMA has written to the Done Queue, it increments the Write Pointer by one
dword. A check must be made to make sure the incremented address does not exceed the Transmit Done
Queue End Address. If the incremented address does exceed this address, then the incremented write
pointer will be set equal to 0000h (i.e. the Base Address).
Status Bits / Interrupts
On writes to the Done Queue by the DMA, the DMA will set the Status Bit for Transmit DMA Done
Queue Write (TDQW) in the Status Register for DMA (SDMA). The Host can configure the DMA to
either set this status bit on each write to the Done Queue or only after multiple (from 2 to 128) writes.
The Host controls this by setting the TDQT0 to TDQT2 bits in the Transmit DMA Queues Control
(TDMAQ) register. See the description of the TDMAQ register at the end of this section for more details.
Done Queue DMA Write Pointer
Done Queue Host Read Pointer
Maximum of 65536
Done Queue Descriptors
dmatdq
Base + End Address
Base + 00h
Base + 04h
Base + 08h
Base + 0Ch
Base + 10h
Base + 14h
Done Queue Descriptor
Done Queue Descriptor
Done Queue Descriptor
Done Queue Descriptor
Done Queue Descriptor
Done Queue Descriptor
Done Queue Descriptor
137 of 203
Host Processed
Host Processed
Host Processed
DMA Readied
DMA Readied
DMA Readied
DMA Readied
Acronym
TDQBA0
TDQBA1
TDQWP
TDQRP
TDQEA
TDQFFT
Address
083Ch
0830h
0834h
0840h
0838h
0844h
DS3134