Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 89

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

Table 44. Z80230 AC Characteristics (Continued)
PS005303-0907
No
34
35
36
37
38
39
40
41
42
43
44
Note:
1. Parameter does not apply to Interrupt Acknowledge transactions.
2. Parameter applies only between transactions involving the ESCC.
3. Float delay is defined as the time required for a ±0.5V change in the output with a maximum DC load and a min-
4. Open-drain output, measured with open-drain test load.
5. Parameter is system-dependent. For any Zilog ESCC in the daisy chain. TdAS(DSA) must be greater than the
6. Parameter applies only to a Zilog ESCC pulling INT Low at the beginning of the Interrupt Acknowledge transac-
7. Internal circuitry allows for the reset provided by the Z8 to be recognized as a reset by the Z-ESCC. All timing
8. Units in nanoseconds (ns).
9. Units inTcPc
imum AC load.
sum of TdAS(IEO) for the highest priority device in the daisy chain. TsIEI(DSA) for the Zilog ESCC, and
TdIEI(IEO) for each device separating them in the daisy chain.
tion.
references assume 2.0V for a 1 and 0.8V for a logic 0.
Symbol
TdIEI(IEO)
TdAS(IEO)
TdDSA(INT) DS Fall (Acknowledge) to INT
TdDS(ASQ)
TdASQ(DS)
TwRES
TwPCl
TwPCh
TcPc
TrPC
TfPC
Figure 28
Parameter
IEI to IEO Delay
AS Rise to IEO Delay
Inactive Delay
DS Rise to AS Fall Delay for No
Reset
AS Rise to DS Fall Delay for No
Reset
AS and DS Coincident Low for
Reset7
PCLK Low Width
PCLK High Width
PCLK Cycle Time
PCLK Rise Time
PCLK Fall Time
illustrates the Z80230 system timing diagram.
40
Min.
15
15
100
40
100
10 MHz
Max.
90
175
450
100
1000
2000
10
10
Min.
10
10
75
26
26
61
Product Specification
16 MHz
Electrical Characteristics
Max
45
80
200
1000
1000
2000
5
5
Z85230/Z80230
Notes
8
6
4, 8
8
8
8
8
8
8
8
8
84