Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 23

IC 8MHZ ESCC 40-DIP

Z8523008PSG

Manufacturer Part Number
Z8523008PSG
Description
IC 8MHZ ESCC 40-DIP
Manufacturer
Zilog
Datasheet

Specifications of Z8523008PSG

Controller Type
Serial Communications Controller (SCC)
Interface
Bus
Voltage - Supply
4.5 V ~ 5.5 V
Current - Supply
4mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Through Hole
Package / Case
40-DIP (0.620", 15.75mm)
Operating Supply Voltage
5 V
Supply Current (max)
9 mA
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
Through Hole
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-3917
Z8523008PSG

Available stocks

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Quantity
Price
Part Number:
Z8523008PSG
Manufacturer:
Zilog
Quantity:
177
Z85230/Z80230
Product Specification
18
NRZ, NRZI, or FM coding may be used in any 1X mode. The parity options available in
ASYNCHRONOUS mode are also available in SYNCHRONOUS mode. However, parity
checking is not normally used for SDLC because CRC checking is more robust.
SDLC LOOP Mode
The ESCC supports SDLC LOOP mode as well as normal SDLC. In SDLC LOOP mode,
a primary controller station manages the message traffic flow on the loop and any number
of secondary stations. In SDLC LOOP mode, the ESCC performs the functions of a sec-
ondary station. An ESCC operation in regular SDLC mode may act as a controller (see
Figure 10). SDLC LOOP mode is selected by setting WR10 bit 1 to 1.
Controller
Secondary #1
Secondary #4
Secondary #2
Secondary #3
Figure 10. SDLC LOOP mode
A secondary station in an SDLC LOOP mode always monitors the messages sent around
the loop and passes these messages to the rest of the loop, retransmitting them with a one-
bit time delay. The secondary station places its own message in the loop only at specific
times. The controller indicates that the secondary stations can transmit messages by send-
ing a special character, called EOP, around the loop. The EOP character has a bit pattern
, the same pattern as an
character in normal HDLC. This bit pattern is
11111110
Abort
unique and easily recognized, because of the zero insertion in the message.
When a secondary station has a message to transmit and recognizes an EOP on the line, it
changes the last binary 1 of the EOP to a 0 before transmission. This action changes the
EOP into a flag sequence. The secondary station now places its message on the loop and
terminates the message with an EOP. Any secondary stations further down the loop with
messages to transmit appends their messages to the message of the first secondary station
using the same process. Secondary stations without any messages to transmit merely echo
the incoming message. All secondary stations are prohibited from placing messages on the
loop except upon recognizing an EOP. In SDLC LOOP mode, NRZ, NRZI or FM coding
can be used.
PS005303-0907
Functional Description

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