Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 11

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

PS005303-0907
Note:
Pin Descriptions Exclusive to the Z85230
Pin Descriptions Exclusive to the Z80230
WR and RD going Low simultaneously is interpreted as a Reset.
INT (Interrupt (Output, Open-Drain, Active Low)).
requests an interrupt. The INT is an open-drain output.
INTACK (Interrupt Acknowledge (Input, Active Low)).
cates that an Interrupt Acknowledge Cycle is in progress. During this cycle, the ESCC
interrupt daisy chain is resolved. The device can return an interrupt vector that may be
encoded with the type of interrupt pending. During the acknowledge cycle, if IEI is High,
the ESCC places the interrupt vector on the data bus when RD goes active for the Z85230,
or when DS goes active for the Z80230. INTACK is latched by the rising edge of PCLK.
The pin description for pins exclusive to Z85230 is provided below:
Pins D7–D0 (Data Bus (Bidirectional, tristate)).
and from the Z85230.
CE (Chip Enable (Input, Active Low)).
operation.
RD ((Read (input, Active Low)).
Z85230 is selected, enables the Z85230’s bus drivers. During the Interrupt Acknowledge
cycle, RD gates the interrupt vector onto the bus if the Z85230 is the highest priority
device requesting an interrupt.
WR (Write (Input, Active Low)).
operation, which indicates that the CPU writes command bytes or data to the Z85230 write
registers.
A/B (Channel A/Channel B (Input)).
Write operation occurs. A High selects Channel A and a Low selects Channel B.
D/C (Data/Control Select (Input)).
to or from the Z85230. A High indicates data transfer and a Low indicates a command
transfer.
The pin description for pins exclusive to Z80230 is provided below:
AD7–AD0 (Address/Data Bus (Bidirectional, Active High, tristate)).
plexed lines carry register addresses to the Z80230 as well as data or control information
to and from the Z80230.
R/W (Read/Write (Input, Read Active High)).
performed is a Read or Write operation.
This pin indicates a Read operation and, when the
When the Z85230 is selected, this pin denotes a Write
This signal defines the type of information transferred
This pin selects the channel in which the Read or
This pin selects the Z85230 for a Read or Write
This pin specifies if the operation to be
These pins carry data and commands to
This pin activates when the ESCC
This pin is a strobe which indi-
Product Specification
These multi-
Z85230/Z80230
Pin Descriptions
6