Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 30

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

PS005303-0907
Bit 3 (Receive FIFO Interrupt Level)
This bit sets the interrupt level of the receive FIFO. If this bit is set to 1, the receive data
available bit is asserted when the receive FIFO is half full (4 bytes available). If this bit is
reset to 0, the Receive Data Available interrupt is requested when all bytes are set. For
more information, see
Bit 2 (Automatic RTS Pin Deassertion)
This bit controls the timing of the deassertion of the RTS pin in SDLC mode. If this bit is
1 and WR5 bit 1 is set to 0 during the transmission of an SDLC frame, the deassertion of
the RTS pin is delayed until the last bit of the closing flag clears the TxD pin. The RTS pin
is pulled High after the rising edge of the transmit clock cycle from the last bit of the clos-
ing flag. This action implies that the ESCC must be programmed for Flag on Underrun
(WR10 bit 2 is 0) for the RTS pin to deassert at the end of the frame. This feature works
independently of the programmed Transmitter Idle state. In SYNCHRONOUS mode other
than SDLC, the RTS pin immediately follows the state programmed into WR5 bit 1. When
WR7’ bit 2 is set to 0, the RTS follows the state of WR5 bit 1.
Bit 1 (Automatic EOM Reset)
If this bit is 1, the ESCC automatically resets the Tx Underrun/EOM latch and presets the
transmit CRC generator to its programmed preset state (per values set in WR5 bit 2 and
WR10 bit 7). Therefore, it is not necessary to issue the Reset Tx Underrun/EOM Latch
command when this feature is enabled.
Bit 0 (Automatic Tx SDLC Flag)
If this bit is 1, the ESCC automatically transmits an SDLC flag before transmitting data.
This action removes the requirement to reset the Mark Idle bit (WR10 bit 3) before writing
data to the transmitter.
WAIT/REQ
DTR/REQ
D7–D0
Figure 12. DMA Request on Transmit Deactivation Timing
WR
8-Byte Receive FIFO
Transmit Data
WR7 bit 4 =1
WR7 bit 4 = 0
on page 22.
Z80230/Z85230 Enhancements
Product Specification
Z85230/Z80230
25