Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 31

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

PS005303-0907
CRC Reception in SDLC Mode
TxD Forced High in SDLC with NRZI Encoding When Marking Idle
Improved Transmit Interrupt Handling
Historically, the SCC latched the databus on the falling edge of WR. However, as many
CPUs do not guarantee that the databus is valid when the WR pin goes Low, Zilog modi-
fied the databus timing to allow a maximum delay of 20 nS from the WR signal going
active Low to the latching of the databus.
In SDLC mode, the entire CRC is clocked into the receive FIFO. The ESCC completes
clocking in the CRC to allow it to be retransmitted or manipulated software. In the SCC,
when the closing flag is recognized, the contents of the receive shift register are immedi-
ately transferred to the receive FIFO, resulting in the loss of the last two bits of the CRC.
In the ESCC, it is not necessary to program this feature. When the closing flag is detected,
the last two bits of the CRC are transferred into the receive FIFO. In all other
SYNCHRONOUS mode, the ESCC does not clock in the last two CRC bits (same as the
SCC).
When the ESCC is programmed for SDLC mode with NRZI data encoding and Mark Idle
(WR10 bit 6 is 0, bit 5 is 1, bit 3 is 1), the TxD pin is automatically forced High when the
transmitter enters the Mark Idle state. There are several different ways for the transmitter
to enter the Idle state. In each of the following cases the TxD pin is forced High when the
Mark Idle condition is reached:
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The Force High feature is disabled when the Mark Idle bit is set to 0.
This feature is used in combination with the automatic SDLC opening flag transmission
feature, WR7’ bit 0 is 1, to assure that data packets are formatted correctly. In this case, the
CPU is not required to issue any commands. If WR7’ bit 0 is 0, as on the SCC, the Mark
Idle bit (WR10 bit 3), is set to 1, to enable flag transmission before an SDLC packet trans-
mits.
The ESCC latches the TBE interrupt because the CRC is loaded into the Transmit Shift
register even if the TBE interrupt, due at the last data byte, has not been reset. The end of a
Data, CRC, flag, and Idle
Data, flag, and Idle
Data, abort (on underrun), and Idle
Data, abort (command), and Idle
Idle flag and command to Idle Mark
Z80230/Z85230 Enhancements
Product Specification
Z85230/Z80230
26