Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 113

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

Index
A
abort character
absolute maximum ratings
AC characteristics
AC characteristics table, Z85230
AC characteristics, Z85230
asynchronous receive mode
auto echo and logical loopback
auto enable
automatic EOM reset
B
baud rate generator
bisync
block transfer, CPU/DMA
C
capacitance
character
code
command
counter
CRC problem
CRC reception in SDLC mode
Customer Feedback Form
PS005303-0907
abort 18
EOP 18
NRZ 18
NRZI 18
reset highest IUS 28
reset Tx CRC generator 28
reset Tx/underrun latch 28
transmit clock 5
description 103
solution 103
4, 16
4
76
18
77
19
28
112
75
15
86
4
26
21
89
D
data communications capabilities
data encoding
DC characteristics
default RR0 value problem
default RR10 value problem
device type identification
diagram
description 102
solution 102
description 103
solution 103
40-pin DIP package 104
44-pin PLCC package 105
automatic RTS deactivation 101
cycle timing, Z85230 88
data encoding methods 20
detecting 5-or 7-bit characters 16
DPLL Outputs 27
ESCC protocols 15
general timing, Z80230 80
general timing, Z85230 93
interrupt
interrupt
interrupt acknowledge timing, Z80230 79
interrupt acknowledge timing, Z85230 88
interrupt priority schedule 13
read cycle timing, Z80230 71
read cycle timing, Z85230 73
read/write timing, Z80230 78
read/write timing, Z85230 87
receive data path 9
reset timing, Z80230 79
reset timing, Z85230 88
resetting highest IUS from lower priority
SDLC frame status FIFO 29
SDLC loop 18
standard and open-drain test conditions 76
Z80230 72
Z85230 74
100
20
acknowledge
acknowledge
77
Product Specification
24
15
cycle
cycle
timing,
timing,
Index
108