Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 104

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

PS005303-0907
IUS Problem Solutions
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•
•
The following methods can be used to work around the previously described problems.
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•
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When the SDLC FIFO is enabled and Receive Interrupts on Special Conditions Only is
selected, software checks that there is a Receive Character Available interrupt, which is
generated by DMA reading an EOF character, and before issuing the
IUS
The processor does not acknowledge this interrupt because it is servicing another
interrupt.
The processor finishes servicing the other interrupt and uses the
command.
The IP bit reset corresponding to the EOF, and the EOF interrupt is lost.
Alternate Operating Mode–A similar operating mode can be used to achieve the same
functionality with minimum code modifications. The ESCC must operate in Receive
Interrupts on First Character and Special Condition, instead of Receive Interrupt on
Special Condition Only.
In this mode, the Anti-Lock feature is not enabled. The FIFO is locked after the last
character of a frame has been transferred, and the interrupt condition does not
disappear until after an
Highest IUS
Daisy Chain– This workaround uses the following two conditions:
–
–
If both conditions are satisfied, allowing nested interrupts can solve the problem.
The processor servicing an interrupt on the daisy chain must be interruptible again
from another interrupt of higher priority on that same daisy chain.
RR7 Register–This workaround is applicable if the EOF interrupt is used only to
notify another part of the software that there has been another frame received:
–
–
command. Otherwise, the EOF interrupt conditions are cleared by that command.
The EOF interrupt is the highest priority interrupt if only one channel is used.
Channel A is the only channel issuing interrupts.
Read RR7 after issuing the
Check bit 6 of RR7. This bit, when set, indicates that the SDLC frame
FIFO contains a valid frame. Although one interrupt might have been lost
(IP reset) by the
least one frame is available in the frame FIFO. If bit 6 of RR7 is 1, notify
the concerned part of the software that at least one frame is available in
the frame FIFO.
command can clear any IP bit.
Reset IUS
Error Reset
command, bit 6 of RR7 always indicates that at
Reset IUS
command is issued to the ESCC. No
command.
Product Specification
Reset Highest IUS
Reset Highest
Z80230/Z85230 Errata
Z85230/Z80230
Reset
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