Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 107

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

PS005303-0907
Automatic TxD Forced High Problem Solutions
SDLC FIFO Overflow Problem Description
SDLC FIFO Overflow Problem Solution
Default RR0 Value Problem Description
Default RR0 Value Problem Solution
back frames are sent. The TxD output is automatically forced High for eight bit-times and
the first byte of the second frame is corrupted. In a multiple-frame transmission, a zero (0)
bit is inserted before the opening flag of the second frame.
Send back-to-back frames in FLAG IDLE mode, because the Automatic TxD Forced High
feature creates problems only if all the following conditions are true:
•
•
•
Setting the system in Flag Idle mode (WR10 bit 3 equals 0) in frame transmission allows
back-to-back frames to be sent without any data corruption.
In SDLC mode, bit 7 of RR7 (FIFO Overflow status bit) is set if an 11th frame ends while
the FIFO is full (that is, 10 frames have accumulated in the Status FIFO and have not yet
been read by the processor). Under this circumstance, the status FIFO is locked and no
data can be written to the Status FIFO until bit 7 of RR7 is reset.
If the ESCC is set up in ANTI-LOCK mode (that is, the SDKC FIFO is used when
Receive Interrupts on Special Condition Only is enabled), the only method of resetting bit
7 of RR7(the FIFO Overflow bit) is to reset and set WR15 bit 2 (SDLC FIFO Enable Bit).
This action causes the SDLC FIFO to reset and all the SDLC frame information is lost.
With no Anti-Lock feature, the FIFO Overflow status bit is reset if the SDLC FIFO is
read.
If the ESCC is in NRZI and Mark Idle in back-to-back frame transmission, (one the FIFO
Overflow bit RR7 bit 7) is set, the only method of resetting the status is to reset and set
WR15 bit 2. This action causes the SDLC FIFO to reset and the unprocessed frame infor-
mation stored in the SDLC FIFO is lost.
Do not use Receive Interrupts on Special Conditions Only and Mark Idle if there is a pos-
sibility of Status FIFO Overflow.
RR7 bit 7, the Break/Abort status bit, does not always clear after reset.
Ignore the first bit 7 value read from RR0 after reset.
Back-to-back frame transmission
NRZI
Mark Idle
Product Specification
Z80230/Z85230 Errata
Z85230/Z80230
102