Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 33

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

PS005303-0907
Software Interrupt Acknowledge
Fast SDLC Transmit Data Interrupt Response
SDLC FIFO Frame Status Enhancement
The Z80230/Z85230 interrupt acknowledge cycle can be initiated using software. If Write
Register 9 (WR9 bit 5 is 1), Read Register 2 (RR2) results in an interrupt INTACK cycle,
a software acknowledgment causes the INT pin to go High. The IEO pin goes Low. The
Interrupt Under Service (IUS) latch is set to the highest priority pending interrupt.
When a hardware INTACK signal is desired, a software acknowledge cycle requires that a
Reset Highest IUS command be issued in the ISR. If RR2 is read from Channel A, the
unmodified vector is returned. If RR2 is read from Channel B, then the vector is modified
to indicate the source of the interrupt. The Vector Includes Status (VIS) and No Vector
(NV) bits in WR9 are ignored when WR9 bit 5 is set to 1.
If the INTACK and IEI pins are not used, they are pulled up to V
(2.2 k?, typical).
To more easily facilitate the transmission of back-to-back SDLC frames with a single
shared flag between frames, the ESCC allows data for a second frame to be written to the
transmit FIFO after the Tx Underrun/EOM interrupt occurs. This feature allows applica-
tion software more time to write the data to the transmitter while allowing the current
frame to conclude with CRC and flag. The SCC required that data not be written to the
transmitter until a TBE interrupt is generated after the CRC completed transmission.
If data is written to the transmit FIFO after the Transmit Underrun/EOM interrupt is issued
but before the TBE interrupt is issued, the Automatic EOM Reset function is enabled
(WR7’ bit 1 is 1). Consequently, the commands Reset Tx/Underrun EOM Latch and Reset
Tx CRC Generator must never be used.
When used with a DMA controller, the ESCC SDLC Frame Status FIFO enhancement
maximizes the ESCC’s ability to receive high-speed, back-to-back SDLC messages. It
minimizes frame overruns due to CPU latencies in responding to interrupts. The feature
(illustrated in
•
•
•
The 10 x 19 bits status FIFO is separate from the 8-byte receive data FIFO.
When the enhancement is enabled, the status in Read Register 1 (RR1) and byte count for
the SDLC frame are stored in the 10- x 19-bit status FIFO. This action allows the DMA
10-bit deep by 19-bit wide status FIFO
14-bit receive byte counter
Control logic
Figure
15) includes a:
Z80230/Z85230 Enhancements
Product Specification
CC
through a resistor
Z85230/Z80230
28