Z8523008PSG Zilog, Z8523008PSG Datasheet - Page 18

• Manufacturer Part Number: Z8523008PSG
• Description: IC 8MHZ ESCC 40-DIP
• Manufacturer: Zilog

Specifications of Z8523008PSG

• Controller Type: Serial Communications Controller (SCC)
• Interface: Bus
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 4mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Through Hole
• Package / Case: 40-DIP (0.620", 15.75mm)
• Operating Supply Voltage: 5 V
• Supply Current (max): 9 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-3917; Z8523008PSG

Z85230/Z80230
Product Specification
13
Peripheral
Peripheral
Peripheral
+5V
IEI A7–A0INT INTACKIEO
IEI A7–A0 INTINTACKIEO
IEI A7–A0INTINTACK
+5V
A7–A0
INT
INTACK
Figure 7. ESCC Interrupt Priority Schedule
The ESCC can also execute an Interrupt Acknowledge cycle using software. Sometimes it
is difficult to create the INTACK signal with the necessary timing to acknowledge inter-
rupts and allow the nesting of interrupts. In such cases, interrupts can be acknowledged
with a software command to the ESCC. For more information,
Z80230/Z85230 Enhance-
ments
on page 22
Interrupt Pending (IP) bits signal a need for interrupt servicing. When an IP bit is 1 and the
IEI input is High, the INT output is pulled Low, requesting an interrupt. In the ESCC, if an
IE bit is not set, then the IP for that source is never set. The IP bits are read in RR3A.
The Interrupt Under Service (IUS) bits signal that an interrupt request is being serviced. If
IUS is set to 1, all interrupt sources of low priority in the ESCC and external to the ESCC
are prevented from requesting interrupts. The internal interrupt sources are inhibited by
the state of the internal daisy chain, while lower priority devices are inhibited by setting
IEO Low for subsequent peripherals. An IUS bit is set during an Interrupt Acknowledge
cycle if there are no higher priority devices requesting interrupt.
There are 3 type of interrupts as listed below:
1. Transmit
2. Receive
3. External/Status
Each interrupt type is enabled under program control with Channel A having higher prior-
ity than Channel B, and with Transmit, Receive, and External/Status interrupts prioritized
in that order within each channel. When the Transmit interrupt is enabled (WR1 bit 1 is 1),
the occurrence of the interrupt depends on the state of WR7’ bit 5. If WR7’ bit 5 is 0, the
CPU is interrupted when the top byte of the transmit FIFO becomes empty. If WR7’ bit 5
is 1, the CPU is interrupted when the transmit FIFO becomes completely empty. The
transmit interrupt occurs when the data in the exit location of the Transmit FIFO loads into
the Transmit Shift Register and the Transmit FIFO becomes completely empty. This con-
dition means that there must be at least one character written to the Tx FIFO for it to
become empty.
PS005303-0907
Functional Description