EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 960

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–10
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 6 of 10)
Stratix IV Device Handbook Volume 3
What is the channel width?
ALTGX Setting
Basic
Deterministic Latency
This option determines the FPGA fabric-Transceiver
interface width.
■
■
Basic (PMA Direct)
This option determines the FPGA fabric-Transceiver
interface width.
■
■
GIGE
This option determines the FPGA fabric-Transceiver
interface width. In GIGE mode, only 8 bits are allowed.
(OIF) CEI PHY Interface
This option selects the FPGA fabric-Transceiver width. In
(OIF) CEI PHY Interface mode, only 32 bits are allowed.
PCI Express (PIPE)
This option determines the FPGA fabric-Transceiver
interface width.
■
■
SDI
This option determines the FPGA fabric-Transceiver
interface width:
■
■
■
■
Serial RapidIO
The channel width is fixed to 16 in Serial RapidIO mode.
Single-width mode—Selecting 8 or 10 bits bypasses
the byte serializer/deserializer. Selecting 16 or 20 bits
uses the byte serializer/deserializer.
Double-width mode—Selecting 16 or 20 bits
bypasses the byte serializer/deserializer. Selecting 32
or 40 bits uses the byte serializer/deserializer.
Single-width mode—You can select 8 or 10 bits.
Double-width mode— You can select 16 or 20 bits.
In PCI Express (PIPE) Gen1 (2.5 Gbps) mode, 8 and
16 bits are allowed.
In PCI Express (PIPE) Gen2 (5 Gbps) mode, only 16
bits are allowed.
HD mode—10-bit and 20-bit channel widths are
allowed.
3G mode—only 20-bit channel width is allowed.
10-bit configuration—the byte serializer is not used.
20-bit configuration—the byte serializer is used.
Description
Chapter 1: ALTGX Transceiver Setup Guide
© November 2009 Altera Corporation
“Byte Serializer” and “Byte
Deserializer” sections in the
Stratix IV Transceiver
Architecture
Reference
chapter.
Parameter Settings