EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 530
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–92
Stratix IV Device Handbook Volume 2
1
Byte Ordering Block in Single-Width Modes
Table 1–33
Table 1–33. Single Width Functional Modes for the Byte Ordering Block
For more information about configurations that allow the byte ordering block in the
receiver datapath, refer to
The Quartus II software automatically configures the byte ordering pattern and byte
ordering PAD pattern for SONET/SDH OC-48 functional mode. For more
information, refer to
In Basic single-width mode, you can program a custom byte ordering pattern and
byte ordering PAD pattern in the ALTGX MegaWizard Plug-In Manager.
shows the byte ordering pattern length allowed in Basic single-width mode.
Table 1–34. Byte Ordering Pattern Length in Basic Single-Width Mode
SONET/SDH OC-48
Basic single-width mode with:
Basic single-width mode with:
Basic single-width mode with:
■
■
■
Basic single-width mode with:
■
■
■
Note to
(1) If a /Kx.y/ control code group is selected as the byte ordering pattern, the MSB of the 9-bit byte ordering pattern
16-bit FPGA fabric-transceiver interface
No 8B/10B decoder
Word aligner in manual alignment mode
16-bit FPGA fabric-transceiver interface
8B/10B decoder
Word aligner in automatic synchronization
state machine mode
must be 1'b1. If a /Dx.y/ data code group is selected as the byte ordering pattern, the MSB of the 9-bit byte ordering
pattern must be 1'b0. The least significant 8 bits must be the 8B/10B decoded version of the code group used for
byte ordering.
Table
Functional Modes
lists the single-width byte ordering block functional modes.
1–34:
Functional Mode
“OC-48 Byte Ordering” on page
“Basic Single-Width Mode Configurations” on page
■
■
■
■
■
■
16-bit FPGA fabric-transceiver interface
No 8B/10B decoder (8-bit PMA-PCS interface)
Word aligner in manual alignment mode
16-bit FPGA fabric-transceiver interface
8B/10B decoder
Word aligner in automatic synchronization state machine
mode
Byte Ordering Pattern
9 bits
Length
8 bits
Chapter 1: Stratix IV Transceiver Architecture
Descriptions
(1)
1–174.
—
© March 2010 Altera Corporation
Transceiver Block Architecture
Byte Ordering PAD
Pattern Length
8 bits
9 bits
Table 1–34
1–110.
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