EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 497

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Figure 1–47. Word Aligner Configured in Bit-Slip Mode
© March 2010 Altera Corporation
rx_patterndetect
rx_dataout[7:0]
rx_datain
rx_clkout
rx_bitslip
Bit-Slip Mode Word Aligner with 8-Bit PMA-PCS Interface Modes
Basic single-width mode with 8-bit PMA-PCS interface width allows the word aligner
to be configured in bit-slip mode. The word aligner operation is controlled by the
input signal rx_bitslip in bit-slip mode. At every rising edge of the rx_bitslip
signal, the bit-slip circuitry slips one bit into the received data stream, effectively
shifting the word boundary by one bit. In bit-slip mode, the word aligner status signal
rx_patterndetect is driven high for one parallel clock cycle when the received
data after bit-slipping matches the 16-bit word alignment pattern programmed in the
ALTGX MegaWizard Plug-In Manager.
You can implement a bit-slip controller in the FPGA fabric that monitors either the
rx_dataout signal and/or the rx_patterndetect signal and controls the
rx_bitslip signal to achieve word alignment.
Figure 1–47
this example, consider that 8'b11110000 is received back-to-back and
16'b0000111100011110 is specified as the word alignment pattern. A rising edge on the
rx_bitslip signal at time n + 1 slips a single bit 0 at the MSB position, forcing the
rx_dataout to 8'b01111000. Another rising edge on the rx_bitslip signal at time
n + 5 forces rx_dataout to 8'b00111100. Another rising edge on the rx_bitslip
signal at time n + 9 forces rx_dataout to 8'b00011110. Another rising edge on the
rx_bitslip signal at time n + 13 forces the rx_dataout to 8'b00001111. At this
instance, rx_dataout in cycles n + 12 and n + 13 is 8'b00011110 and 8'b00001111,
respectively, which matches the specified 16-bit alignment pattern
16'b0000111100011110. This results in the assertion of the rx_patterndetect signal.
11110000
n
shows an example of the word aligner configured in bit-slip mode. For
n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8 n + 9 n + 10 n + 11 n + 12 n + 13 n + 14
01111000
11110000
00111100
00011110
Stratix IV Device Handbook Volume 2
00001111
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