EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 230

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–8
Table 7–3. Number of DQS/DQ Groups in Stratix IV Devices per Side (Part 2 of 2)
Stratix IV Device Handbook Volume 1
EP4SE820
EP4SGX290
EP4SGX360
EP4SGX530
EP4S100G3
EP4S100G4
EP4S100G5
Notes to
(1) These numbers are preliminary until the devices are available.
(2) Some of the ×4 groups may use R
(3) To interface with a ×36 QDR II+/QDR II SRAM device in a Stratix IV FPGA that does not support the ×32/×36 DQS/DQ group, refer
(4) These ×32/×36 DQS/DQ groups have 40 pins instead of 48 pins per group. BWSn pins cannot be placed within the same DQS/DQ
to
group as the write data pins because of insufficient pins available.
“Combining ×16/×18 DQS/DQ Groups for a ×36 QDR II+/QDR II SRAM Interface” on page
Device
Table
7–3:
1760-pin
FineLine BGA
1932-pin
FineLine BGA
1932-pin
FineLine BGA
Package
UP
and R
DN
pins. You cannot use these groups if you use the Stratix IV calibrated OCT feature.
Top/Bottom
Top/Bottom
Top/Bottom
Right/Left
Right/Left
Right
Side
Left
×4
40
44
29
38
38
8
7
(2)
Chapter 7: External Memory Interfaces in Stratix IV Devices
×8/×9
18
22
13
18
18
2
1
7–27.
(Note 1)
×16/×18
10
6
4
8
0
8
0
© March 2010 Altera Corporation
Memory Interfaces Pin Support
×32/×36
0
4
0
4
0
4
0
(3)
Figure 7–17
Figure 7–18
Figure 7–19
Refer to: