EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 527
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 1: Stratix IV Transceiver Architecture
Transceiver Block Architecture
Figure 1–76. 8B/10B Decoder 10-Bit Control Code Group
© March 2010 Altera Corporation
1
Control Code Group Detection
The cascaded 8B/10B decoder indicates whether the decoded 16-bit code group is a
data or control code group on the 2-bit rx_ctrldetect[1:0] port. The
rx_ctrldetect[0] signal is driven high or low depending on whether decoded
data on the rx_dataout[7:0] port (LSByte) is a control or data code group,
respectively. The rx_ctrldetect[1] signals are driven high or low depending on
whether decoded data on the rx_dataout[15:8] port (MSByte) is a control or data
code group, respectively.
Figure 1–76
group into 8-bit data code group (8'hBC) driven on the rx_dataout port. The
rx_ctrldetect signal is asserted high synchronous with 8'hBC on the
rx_dataout port, indicating that it is a control code group. The rest of the codes
received are data code groups /Dx.y/.
Byte Deserializer
The FPGA fabric-transceiver interface frequency has an upper limit that is stated in
the “Interface Frequency” section in the
functional modes that have a receiver PCS frequency greater than the upper limit
stated in the
status signals cannot be forwarded directly to the FPGA fabric because it violates this
upper limit for the FPGA fabric-transceiver interface frequency. In such
configurations, the byte deserializer is required to reduce the FPGA fabric-transceiver
interface frequency to half while doubling the parallel data width. For example, at
3.2 Gbps data rate with a deserialization factor of 10, the receiver PCS datapath runs
at 320 MHz. The 10-bit parallel received data and status signals at 320 MHz cannot be
forwarded to the FPGA fabric because it violates the upper limit for the FPGA
fabric-transceiver interface frequency. The byte serializer converts the 10-bit parallel
received data at 320 MHz into 20-bit parallel data at 160 MHz before forwarding to
the FPGA fabric.
The byte deserializer is required in configurations that exceed the FPGA
fabric-transceiver interface clock upper frequency limit. It is optional in
configurations that do not exceed the FPGA fabric-transceiver interface clock upper
frequency limit.
The byte deserializer operates in two modes:
■
■
Single-width mode
Double-width mode
rx_ctrldetect[1:0]
rx_dataout[15:0]
datain[19:10]
datain[9:0]
shows the 8B/10B decoding of the received 10-bit /K28.5/ control code
DC and Switching Characteristics
clock
16'h8378
D24.3
D3.4
00
16'hBCBC
D28.5
D28.5
01
DC and Switching Characteristics
16'h0F0F
D15.0
D15.0
chapter, the parallel received data and
00
16'h8383
D3.4
D3.4
Stratix IV Device Handbook Volume 2
chapter. In
1–89
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