EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 111
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Shift Modes
© November 2009 Altera Corporation
1
This mode supports the rounding and saturation logic unit because it is configured as
an 18-bit multiplier accumulator. You can use the pipeline registers and output
registers within the DSP block to increase the performance of the DSP block.
Stratix IV devices support the following shift modes for 32-bit input only:
■
■
■
■
■
You can switch shift mode between these modes using the dynamic rotate and shift
control signals.
You can use shift mode in a Stratix IV device by using a soft embedded processor such
as Nios
shift mode configuration.
Shift mode makes use of the available multipliers to logically or arithmetically shift
left, right, or rotate the desired 32-bit data. You can configure the DSP block similar to
the independent 36-bit multiplier mode to perform the shift mode operations.
Arithmetic shift right requires a signed input vector. During an arithmetic shift right,
the sign is extended to fill the MSB of the 32-bit vector. The logical shift right uses an
unsigned input vector. During a logical shift right, zeros are padded in the MSBs,
shifting the 32-bit vector to the right. The barrel shifter uses unsigned input vector
and implements a rotation function on a 32-bit word length.
Two control signals, rotate and shift_right, together with the signa and signb
signals, determine the shifting operation.
operations.
Arithmetic shift left, ASL[N]
Arithmetic shift right, ASR[32-N]
Logical shift left, LSL[N]
Logical shift right, LSR[32-N]
32-bit rotator or barrel shifter, ROT[N]
®
II to perform the dynamic shift and rotate operation.
Table 4–5
shows examples of shift
Stratix IV Device Handbook Volume 1
Figure 4–20
shows the
4–29
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