EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 1090
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
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Chapter 1: DC and Switching Characteristics for Stratix IV Devices
Switching Characteristics
Table 1–22. Transceiver Specifications for Stratix IV GX Devices (Part 3 of 9)
November 2010 Altera Corporation
reconfig_clk clock
frequency
Delta time between
reconfig_clks
Transceiver block
minimum power-down
(gxb_powerdown)
pulse width
Receiver
Supported I/O
Standards
Data rate (Single width,
non-PMA Direct)
Data rate (Double
width, non-PMA Direct)
Data rate (Single width,
PMA Direct)
Data rate (Double
width, PMA Direct)
Absolute V
receiver pin
Operational V
receiver pin
Absolute V
receiver pin
Maximum peak-to-peak
differential input voltage
V
device configuration
Maximum peak-to-peak
differential input voltage
V
device configuration
ID
ID
(diff p-p) before
(diff p-p) after
Description
Symbol/
MAX
MIN
(3)
MAX
for a
for a
for a
(17)
clock frequency
reconfiguration
V
V
Conditions
setting
ICM
Dynamic
ICM
setting
= 0.82 V
—
—
—
—
—
—
—
—
—
—
=1.1 V
(4)
1000
1000
37.5
-0.4
Min
2.5/
600
600
—
—
—
—
—
—
(2)
1
–2 Commercial
Speed Grade
1.4 V PCML, 1.5 V PCML, 2.5 V PCML, LVPECL, LVDS
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
3750
8500
3250
6500
Max
1.6
1.5
1.6
2.7
1.6
50
—
—
2
1000
1000
37.5
Min
2.5/
600
600
-0.4
Commercial/Industrial
—
—
—
—
—
—
(2)
1
Speed Grade
–2× Commercial
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
and
–3
Stratix IV Device Handbook Volume 4
(1)
3750
6500
3250
6500
Max
1.6
1.5
1.6
2.7
1.6
50
—
—
2
1000
1000
Commercial/Industrial
37.5
Min
2.5/
-0.4
600
600
—
—
—
—
—
—
(2)
1
Speed Grade
Typ
—
—
—
—
—
—
—
—
—
—
—
—
—
–4
1–16
3750
6375
3250
6375
Max
(20)
1.6
1.5
1.6
2.7
1.6
50
—
—
2
Mbps
Mbps
Mbps
Mbps
Unit
ms
—
µs
V
V
V
V
V
V
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