EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 572

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–134
Figure 1–109. Power State Transition from the P0 to P2 Power State
Stratix IV Device Handbook Volume 2
pipephydonestatus
powerdn[1:0]
Parallel
Clock
The PCI Express (PIPE) interface block indicates successful power state transition by
asserting the pipephydonestatus signal for one parallel clock cycle as specified in
the PCI Express (PIPE) specification. The PHY-MAC layer must not request any
further power state transition until the pipephydonestatus signal has indicated
the completion of the current power state transition request.
Figure 1–109
state.
The PCI Express (PIPE) specification allows the PCI Express (PIPE) interface to
perform protocol functions; for example, receiver detect, loopback, and beacon
transmission, in specified power states only. This requires the PHY-MAC layer to
drive the tx_detectrxloopback and tx_forceelecidle signals appropriately
in each power state to perform these functions.
PHY-MAC layer must drive on the tx_detectrxloopback and
tx_forceelecidle signals in each power state.
Table 1–50. Logic Levels for tx_detectrxloopback and tx_forceelecidle in Different Power States
Receiver Status
The PCI Express (PIPE) specification requires the PHY to encode the receiver status on
a 3-bit RxStatus[2:0] signal. This status signal is used by the PHY-MAC layer for
its operation.
The PCI Express (PIPE) interface block receives status signals from the transceiver
channel PCS and PMA blocks and encodes the status on the 3-bit output signal
pipestatus[2:0] to the FPGA fabric. The encoding of the status signals on
pipestatus[2:0] is compliant with the PCI Express (PIPE) specification and is
listed in
Power State
P0s
P0
P1
P2
2'b00 (P0)
Table
shows an example waveform for a transition from the P0 to P2 power
1–51.
0: normal mode
1: datapath in loopback mode
Don’t care
0: Electrical Idle
1: receiver detect
Don’t care
tx_detectrxloopback
2'b11 (P2)
Table 1–50
Chapter 1: Stratix IV Transceiver Architecture
0: Must be de-asserted
1: Illegal mode
0: Illegal mode
1: Must be asserted in this state
0: Illegal mode
1: Must be asserted in this state
De-asserted in this state for sending
beacon. Otherwise asserted.
lists the logic levels that the
© March 2010 Altera Corporation
tx_forceelecidle
Transceiver Block Architecture