EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 668
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 668 of 1145
- Download datasheet (29Mb)
2–4
Figure 2–2. Input Reference Clock Sources in a Transceiver Block
Stratix IV Device Handbook Volume 2
refclk1
refclk0
Figure 2–2
within a transceiver block. One global clock line is available for each CMU PLL and
receiver CDR in a transceiver block. This allows each CMU PLL and receiver CDR to
derive its input reference clock from a separate FPGA CLK input pin.
2
2
shows the input reference clock sources for CMU PLLs and receiver CDRs
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
6
6
6
6
6
6
CMU1 PLL
CDR
CDR
CMU0 PLL
CDR
CDR
Transceiver Block
Chapter 2: Stratix IV Transceiver Clocking
© March 2010 Altera Corporation
CMU1 Channel
CMU0 Channel
Channel 3
Channel 2
Channel 1
Channel 0
Input Reference Clocking
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