EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 61

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
Overview
Table 3–2. TriMatrix Memory Capacity and Distribution in Stratix IV Devices (Part 2 of 2)
TriMatrix Memory Block Types
Parity Bit Support
Byte Enable Support
© March 2010 Altera Corporation
EP4SGX290
EP4SGX360
EP4SGX530
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G3
EP4S100G4
EP4S100G5
Device
1
While the M9K and M144K memory blocks are dedicated resources, the MLABs are
dual-purpose blocks. They can be configured as regular logic array blocks (LABs) or
as MLABs. Ten adaptive logic modules (ALMs) make up one MLAB. Each ALM in an
MLAB can be configured as either a 64 × 1 or a 32 × 2 block, resulting in a 64 × 10 or
32 × 20 simple dual-port SRAM block in a single MLAB.
All TriMatrix memory blocks have built-in parity-bit support. The ninth bit associated
with each byte can store a parity bit or serve as an additional data bit. No parity
function is actually performed on the ninth bit.
All TriMatrix memory blocks support byte enables that mask the input data so that
only specific bytes of data are written. The unwritten bytes retain the previously
written values. The write enable (wren) signals, along with the byte enable
(byteena) signals, control the RAM blocks’ write operations.
The default value for the byte enable signals is high (enabled), in which case writing is
controlled only by the write enable signals. The byte enable registers have no clear
port. When using parity bits on the M9K and M144K blocks, the byte enable controls
all nine bits (eight bits of data plus one parity bit). When using parity bits on the
MLAB, the byte-enable controls all 10 bits in the widest mode.
Byte enables operate in a one-hot fashion, with the LSB of the byteena signal
corresponding to the LSB of the data bus. For example, if you use a RAM block in ×18
mode, with byteena = 01, data[8..0] is enabled, and data[17..9] is disabled.
Similarly, if byteena = 11, both data[8..0] and data[17..9] are enabled. Byte
enables are active high.
You cannot use the byte enable feature when using the error correction coding (ECC)
feature on M144K blocks.
MLABs
10,624
10,624
10624
5824
7072
4560
4560
5824
7072
M9K Blocks
1248
1280
1235
1280
1235
1248
1280
936
936
M144K
Blocks
36
48
64
22
64
22
36
48
64
(Dedicated Memory Blocks Only)
Total Dedicated RAM Bits
13,608
18,144
20,736
14,283
20,736
14,283
13,608
18,144
20,736
(Kb)
Stratix IV Device Handbook Volume 1
(Including MLABs)
Total RAM Bits
17,248
22,564
27,376
17,133
27,376
17,133
17,248
22,564
27,376
(Kb)
3–3