EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 62

IC STRATIX IV FPGA 530K 1152HBGA

EP4SGX530HH35C2N

Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

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Price
Part Number:
EP4SGX530HH35C2N
Manufacturer:
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Quantity:
10 000
Part Number:
EP4SGX530HH35C2N
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ALTERA
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Part Number:
EP4SGX530HH35C2NAD
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Part Number:
EP4SGX530HH35C2NAE
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0
3–4
Figure 3–1. Byte Enable Functional Waveform
Stratix IV Device Handbook Volume 1
current data: q (asynch)
don't care: q (asynch)
contents at a0
contents at a1
contents at a2
address
byteena
inclock
wren
data
Figure 3–1
control the operations of the RAM blocks.
When a byte-enable bit is de-asserted during a write cycle, the corresponding data
byte output can appear as either a “don’t care” value or the current data at that
location. The output value for the masked byte is controllable using the Quartus II
software. When a byte-enable bit is asserted during a write cycle, the corresponding
data byte output also depends on the setting chosen in the Quartus II software.
XXXX
XX
an
FFFF
doutn
doutn
FFFF
shows how the write enable (wren) and byte enable (byteena) signals
10
a0
FFFF
ABXX
ABFF
ABCD
01
a1
XXCD
FFCD
Chapter 3: TriMatrix Embedded Memory Blocks in Stratix IV Devices
11
a2
ABCD
ABCD
ABFF
a0
FFCD
ABFF
ABFF
ABCD
a1
© March 2010 Altera Corporation
XXXX
XX
FFCD
FFCD
a2
ABCD
ABCD
Overview

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