EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 450

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–12
Transceiver Channel Architecture
Figure 1–7. Stratix IV GX and GT Transceiver Datapath
Stratix IV Device Handbook Volume 2
FPGA
Fabric
1
The Stratix IV GT transceiver architecture has the following components:
■
■
■
Four transceiver channels and two CMU channels are located in each transceiver
block on the left and right sides of the device. Each Stratix IV GT device also has two
10G ATX PLLs that support data rates between 9.9 Gbps and 11.3 Gbps. Additionally,
each Stratix IV GT device has two 6G ATX PLLs that support data rates between
2.488 Gbps and 6.5 Gbps, except the EP4S100G5F45 device that has four 6G ATX
PLLs.
The 6G ATX PLL does not support all data rates between 2.488 Gbps and 6.5 Gbps.
Figure 1–7
Each transceiver channel consists of the:
■
■
Regular transceiver channels with PMA and PCS support
CMU channels with PMA-only support
ATX PLL blocks
Transmitter channel, further divided into:
■
■
Receiver channel, further divided into:
■
■
Transmitter channel PCS
Transmitter channel PMA
Receiver channel PCS
Receiver channel PMA
shows the Stratix IV GX and GT transceiver channel datapath.
Compensation
wrclk
TX Phase
FIFO
rdclk
Byte Serializer
wrclk
Receiver Channel PCS
Transmitter Channel PCS
rdclk
Transmitter Channel Datapath
Receiver Channel Datapath
8B/10B Encoder
Chapter 1: Stratix IV Transceiver Architecture
© March 2010 Altera Corporation
Transceiver Block Architecture
Transmitter Channel
Receiver Channel
PMA
PMA