EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 921
![IC STRATIX IV FPGA 530K 1152HBGA](/photos/37/12/371227/1152pin_fbga_sml.jpg)
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
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- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
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Chapter 5: Stratix IV Dynamic Reconfiguration
Dynamic Reconfiguration Controller Port List
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 8 of 13)
© March 2010 Altera Corporation
tx_preemp_2t[4:0]
rx_eqctrl[3:0]
Port Name
(1)
(1)
Output
Input/
Input
Input
This is an optional pre-emphasis write control for the second
post-tap for the transmit buffer. This signal controls both
pre-emphasis positive and its inversion. Depending on what value
you set at this input, the controller dynamically writes the value to
the pre-emphasis control register of the transmit buffer.
The width of this signal is fixed to 5 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 5 bits per channel.
For more information, refer to
Controls” on page
The following values are the legal settings allowed for this signal:
0 represents 0
1-15 represents -15 to -1
16 represents 0
17-31 represents 1 to 15
In PCI Express (PIPE) configuration, set tx_preemp_2t[4:0]
to 5'b00000 when you do a rate switch from Gen 1 to Gen 2 mode.
This is to ensure that tx_preemp_2t[4:0] does not add to the
signal boost when tx_pipemargin and tx_pipedeemph
take affect in PCI Express (PIPE) Gen 2 mode.
For more information, refer to the “Programmable Pre-Emphasis”
section of the
This is an optional write control to write an equalization control
value for the receive side of the PMA.
The width of this signal is fixed to 4 bits if you enable either the Use
'logical_channel_address' port for Analog controls
reconfiguration option or the Use same control signal for all the
channels option in the Analog controls screen. Otherwise, the
width of this signal is 4 bits per channel.
For more information, refer to
Controls” on page 5–13
DC Gain” section of the
Stratix IV Transceiver Architecture
5–13.
Stratix IV Transceiver Architecture
and the “Programmable Equalization and
Description
“Dynamically Reconfiguring PMA
“Dynamically Reconfiguring PMA
Stratix IV Device Handbook Volume 2
(Note
chapter.
3),
(4)
chapter.
5–85
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