EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 699
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 699 of 864
- Download datasheet (11Mb)
Altera Corporation
July 2005
Note to
(1)
Single-port
Multi-port (two-,
three-, or four-port
functions)
Dual-port
Dual-port
Single-port
No clock
Table 10–5. Migration Mode Summary
Configuration
If the SUPPRESS_MEMORY_COUNVERSION_WARNINGS parameter is turned on, the Quartus II software does not
issue these warnings.
Memory
Table
10–5:
All inputs are registered.
All inputs are registered.
Read-enable ports are
unregistered.
Other inputs registered.
Any other unregistered
port except read-enable
ports.
Clock available.
At least one registered
input.
Clock available.
No clock.
Conditions
■
There are differences in power-up behavior between APEX II,
APEX 20K, and Stratix and Stratix GX devices. You should manually
account for these differences to maintain desired operation of the
system.
altram
altrom
lpm_ram_dq
lpm_ram_io
lpm_rom
altdpram
lpm_ram_dp
altqpram
alt3pram
altdpram
lpm_ram_dp
altqpram
alt3pram
altdpram
lpm_ram_dp
altqpram
alt3pram
altram
lpm_ram_dq
lpm_ram_io
altram
altrom
altdpram
altqpram
alt3pram
altdpram
lpm_ram_dq
lpm_ram_io
lpm_rom
lpm_ram_dp
lpm_ram_dp
Transitioning APEX Designs to Stratix & Stratix GX Devices
Megafunctions
Instantiated
Possible
Power-up differences.
Power-up differences.
Mixed-port read- during-
write.
Power-up differences.
Mixed-port read- during-
write.
Read enable will be
registered.
Compile for fitting- evaluation
purposes.
Compile for fitting- evaluation
purposes.
Error – no conversion
possible.
Quartus II Warning
(1)
Stratix Device Handbook, Volume 2
Message(s)
(1)
(1)
Yes
Yes
Yes
No
No
No
Programming
Generated
File
10–15
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