EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 616

IC STRATIX FPGA 20K LE 780-FBGA

EP1S20F780I6N

Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheets

Specifications of EP1S20F780I6N

Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S20F780I6N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
0
Infinite Impulse Response (IIR) Filters
7–38
Stratix Device Handbook, Volume 2
The first DSP block in
adder mode, and the second DSP block is in the four-multipliers adder
mode. For an 18-bit input to the IIR filter, each biquad requires five
multipliers and five adders (two DSP blocks). One of the adders is
implemented using logic elements. Cascading several biquads together
can implement more complex, higher order IIR filters. It is possible to
insert registers in between the biquad stages to improve the performance.
Figure 7–23
biquads in three DSP blocks.
Figure 7–23. Two Cascaded Biquads
a
x[n]
a
a
a
b
b
b
b
a
a
10
20
21
11
12
11
12
21
22
22
shows a 4
Four-multipliers
adder mode
Four-multipliers
adder mode
Two-multipliers
adder mode
th
Figure 7–22
order IIR filter realized using two cascaded
block 3
block 1
block 2
DSP
DSP
DSP
is configured in the two-multipliers
Altera Corporation
September 2004
Second
biquad
biquad
First
y[n]

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