EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 433

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
June 2006
Stratix and Stratix GX devices support both input and output levels for
1.5-V LVCMOS operation.
1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6
The high-speed transceiver logic (HSTL) I/O standard is used for
applications designed to operate in the 0.0- to 1.5-V HSTL logic switching
range. This standard defines single ended input and output specifications
for all HSTL-compliant digital integrated circuits. The single ended input
standard specifies an input voltage range of – 0.3 V V
Stratix and Stratix GX devices support both input and output levels
specified by the 1.5-V HSTL I/O standard. The input clock is
implemented using dedicated differential input buffers. Two single-
ended output buffers are automatically programmed to have opposite
polarity so as to implement a differential output clock. Additionally, the
1.5-V HSTL I/O standard in Stratix and Stratix GX devices is compatible
with the 1.8-V HSTL I/O standard in APEX
devices because the input and output voltage thresholds are compatible.
See
input and output levels with V
Figure 4–1. HSTL Class I Termination
Figure 4–2. HSTL Class II Termination
Figures 4–1
Output Buffer
Output Buffer
and 4–2. Stratix and Stratix GX devices support both
Selectable I/O Standards in Stratix & Stratix GX Devices
V
TT
= 0.75 V
V
50 Ω
REF
V
Z = 50 Ω
REF
REF
= 0.75 V
Z = 50 Ω
= 0.75 V
and V
V
TT
V
Stratix Device Handbook, Volume 2
TT
= 0.75 V
TT
50 Ω
= 0.75 V
.
TM
50 Ω
20KE and APEX 20KC
Input Buffer
Input Buffer
I
V
CCIO
+ 0.3 V.
4–5