EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 532

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Software Support
5–60
Stratix Device Handbook, Volume 2
Notes to
(1)
(2)
(3)
(4)
rx_in[number_of_channels - 1..0]
rx_inclock
rx_pll_enable
rx_data_align
rx_locked
rx_out[Deserialization_factor *
number_of_channels -1..0]
rx_outclock
Table 5–15. LVDS Receiver Ports
This is an optional port.
Only one rx_pll_enable pin is necessary to enable all the PLLs in the device.
This is a non-differential pin.
See
alignment, you must synchronize rx_data_align with rx_outclock.
“Realignment Implementation” on page 5–28
Table
5–15:
Port Name
When you span two I/O banks using cross-bank support, you can route
only two load enable signals total between the plls. When you enable
rx_data_align, you use both rxloadena and txloadena of a PLL.
That leaves no loadena for the second PLL.
The only way you can use the rx_data_align is if one of the following
is true:
■
■
LVDS Receiver Block
You only need to enter the input clock frequency, deserialization factor,
and the input data rate to implement an LVDS receiver block. The
Quartus II software then automatically sets the clock boost (W) factor for
the receiver. In addition, you can also indicate the clock and data
alignment for the receiver or add the pll_enable, rx_data_align,
and rx_locked output ports.
available ports in the LVDS receiver block.
The RX PLL is only clocking RX channels (no resources for TX)
If all channels can fit in one I/O bank
Input
Input
Input
Input
Output
Output
Output
Direction
for more information. For guaranteed performance and data
Input data channel
Reference input clock
Enables fast PLL
Control for the data
realignment circuitry
Fast PLL locked pin
De-serialized data
Internal reference clock
Table 5–15
Function
explains the function of the
Pin
Pin or output from a PLL
Pin (1), (2),
Pin or logic array (1),
(3),
Pin or logic array (1),
Logic array
Logic array
Source/Output Port
(4)
Altera Corporation
Destination
Input Port
(3)
July 2005
(3)