EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 289
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 289 of 864
- Download datasheet (11Mb)
Stratix Device Handbook, Volume 1
Differential HSTL Specifications
DSP
E
EP1S10 Devices
EP1S20 Devices
Altera Corporation
Block Diagram
Block Interconnect Interface
Block Interface
Block Signal Sources & Destinations
Blocks
Input Register Modes
Input Registers
Multiplier
Pipeline/Post Multiply Register
Column Pin
Row Pin
Column Pin
Configuration
Arranged in Columns
in Stratix Devices
Block
Signed Representation
Sub-Block
Sub-Blocks Using Input Shift Register
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
2–60
Connections
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
for 18 x 18-Bit
for 9 x 9-Bit
2–57
Clock
Clock
Clock
2–57
2–70
2–58
External
External
External
4–36
4–37
4–36
4–37
4–38
4–38
4–39
4–40
2–54
2–59
2–60
2–56
2–55
2–53
2–60
2–71
4–15
I/O
I/O
I/O
2–61
Timing
Timing
Timing
2–73
EP1S25 Devices
EP1S30 Devices
EP1S40 Devices
Row Pin
Column Pin
Row Pin
Column Pin
Row Pin
Column Pin
Row Pin
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Fast Regional Clock External I/O Timing
Global
Regional Clock External I/O Timing
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Parameters
Clock
Clock
Clock
Clock
Clock
Clock
External
External
External
External
External
External
4–39
4–40
4–41
4–41
4–42
4–43
4–42
4–43
4–44
4–44
4–45
4–45
4–45
4–46
4–47
4–47
4–48
4–49
4–48
I/O
I/O
I/O
I/O
I/O
I/O
Index–3
Timing
Timing
Timing
Timing
Timing
Timing
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