EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 597
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
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Figure 7–11. Time & Frequency Domain Representations of Interpolation for I = 4
Altera Corporation
September 2004
Implementing High Performance DSP Functions in Stratix & Stratix GX Devices
As an example, CD players use interpolation, where the nominal sample
rate of audio input is 44.1 kilosamples per second. A typical
implementation might have an interpolation (oversampling) factor of 4
generating 176.4 kilosamples per second of oversampled data stream.
Polyphase Interpolation Filters
A direct implementation of an interpolation filter, as shown in
Figure
filter is 16 taps long and a multiplication takes one cycle, then the number
of computations required per cycle is 16 I. Depending on the
interpolation factor (I), this number can be quite big and may not be
achievable in hardware. A polyphase implementation of the low pass
filter can reduce the number of computations required per cycle, often by
a large factor, as will be evident later in this section.
The polyphase implementation “splits” the original filter into I
polyphase filters whose impulse responses are defined by the following
equation:
h
k
7–10, imposes a high computational burden. For example, if the
n
=
h k
+
nI
Stratix Device Handbook, Volume 2
7–19
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