EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 517

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Figure 5–31.
High-Speed
Interface Pin
Locations
Altera Corporation
July 2005
×
2 Data Rate Transmitter Channel with Serialization Factor of 8
Stratix
Logic
Array
PLL
D0, D2,
D1, D3,
×1
D4, D6
D5, D7
×4
×1
Figure 5–30.
Stratix high-speed interface pins are located at the edge of the package to
limit the possible mismatch between a pair of high-speed signals. Stratix
devices have eight programmable I/O banks.
pins and their location relative to the package.
datain_h
outclock
datain_l
dataout
Register
Register
XX
XX
Shift
Shift
×
2 Timing Relation between Parallel Data & Clock
XX
B0
A0
High-Speed Differential I/O Interfaces in Stratix Devices
A0
DDR IOE
B0
DFF
DFF
B1
A1
A1
Stratix Device Handbook, Volume 2
B1
Figure 5–32
B2
A2
A2
dataout
inclock
B2
shows the I/O
B3
A3
A3
5–45