EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 604

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Finite Impulse Response (FIR) Filters
Figure 7–15. Time & Frequency Domain Representations of Decimation for D=4
7–26
Stratix Device Handbook, Volume 2
Polyphase Decimation Filters
Figure 7–14
imposes a high computational burden. For example, if the filter is 16 taps
long and a multiplication takes one cycle, the number of computations
required per cycle is 16 D. Depending on the decimation factor (D), this
number can be quite big and may not be achievable in hardware. A
polyphase implementation of the low pass filter can reduce the number
of computations required, often by a large ratio, as will be evident later in
this section.
The polyphase implementation “splits” the original filter into D
polyphase filters with impulse responses defined by the following
equation.
h
k
n
=
shows a direct implementation of a decimation filter, which
h k
+
nD
Altera Corporation
September 2004