EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 297
![IC STRATIX FPGA 20K LE 780-FBGA](/photos/6/72/67270/544-780-fbga_sml.jpg)
EP1S20F780I6N
Manufacturer Part Number
EP1S20F780I6N
Description
IC STRATIX FPGA 20K LE 780-FBGA
Manufacturer
Altera
Series
Stratix®r
Specifications of EP1S20F780I6N
Number Of Logic Elements/cells
18460
Number Of Labs/clbs
1846
Total Ram Bits
1669248
Number Of I /o
586
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
18460
# I/os (max)
586
Frequency (max)
450.05MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
18460
Ram Bits
1669248
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP1S20F780I6N
Manufacturer:
ALTERA
Quantity:
3 000
- Current page: 297 of 864
- Download datasheet (11Mb)
Contents
Section III. I/O Standards
Chapter 4. Selectable I/O Standards in Stratix & Stratix GX Devices
Altera Corporation
Conclusion ............................................................................................................................................ 3–27
Revision History .................................................................................................................... Section III–1
Introduction ............................................................................................................................................ 4–1
Stratix & Stratix GX I/O Standards .................................................................................................... 4–1
High-Speed Interfaces ......................................................................................................................... 4–15
Stratix & Stratix GX I/O Banks .......................................................................................................... 4–17
DDR Registers ................................................................................................................................. 3–20
PLL ................................................................................................................................................... 3–27
3.3-V Low Voltage Transistor-Transistor Logic (LVTTL) - EIA/JEDEC Standard JESD8-B . 4–2
3.3-V LVCMOS - EIA/JEDEC Standard JESD8-B ........................................................................ 4–3
2.5-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 .......................... 4–3
2.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-5 ..................... 4–3
1.8-V LVTTL Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 .......................... 4–4
1.8-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard EIA/JESD8-7 ..................... 4–4
1.5-V LVCMOS Normal Voltage Range - EIA/JEDEC Standard JESD8-11 ............................ 4–4
1.5-V HSTL Class I & II - EIA/JEDEC Standard EIA/JESD8-6 ................................................. 4–5
1.5-V Differential HSTL - EIA/JEDEC Standard EIA/JESD8-6 ................................................ 4–6
3.3-V PCI Local Bus - PCI Special Interest Group PCI Local Bus Specification Rev. 2.3 ....... 4–6
3.3-V PCI-X 1.0 Local Bus - PCI-SIG PCI-X Local Bus Specification Revision 1.0a ................ 4–7
3.3-V Compact PCI Bus - PCI SIG PCI Local Bus Specification Revision 2.3 .......................... 4–7
3.3-V 1× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 ..... 4–7
3.3-V 2× AGP - Intel Corporation Accelerated Graphics Port Interface Specification 2.0 ..... 4–8
GTL - EIA/JEDEC Standard EIA/JESD8-3 .................................................................................. 4–8
GTL+ .................................................................................................................................................. 4–8
CTT - EIA/JEDEC Standard JESD8-4 ............................................................................................ 4–9
SSTL-3 Class I & II - EIA/JEDEC Standard JESD8-8 .................................................................. 4–9
SSTL-2 Class I & II - EIA/JEDEC Standard JESD8-9A ............................................................. 4–10
SSTL-18 Class I & II - EIA/JEDEC Preliminary Standard JC42.3 ............................................ 4–11
Differential SSTL-2 - EIA/JEDEC Standard JESD8-9A ............................................................. 4–11
LVDS - ANSI/TIA/EIA Standard ANSI/TIA/EIA-644 .......................................................... 4–12
LVPECL ........................................................................................................................................... 4–13
Pseudo Current Mode Logic (PCML) ......................................................................................... 4–13
HyperTransport Technology - HyperTransport Consortium ................................................. 4–14
OIF-SPI4.2 ........................................................................................................................................ 4–15
OIF-SFI4.1 ........................................................................................................................................ 4–15
10 Gigabit Ethernet Sixteen Bit Interface (XSBI) - IEEE Draft Standard P802.3ae/D2.0 ...... 4–16
RapidIO Interconnect Specification Revision 1.1 ....................................................................... 4–16
HyperTransport Technology - HyperTransport Consortium ................................................. 4–17
UTOPIA Level 4 – ATM Forum Technical Committee Standard AF-PHY-0144.001 ........... 4–17
Non-Voltage-Referenced Standards ............................................................................................ 4–24
Voltage-Referenced Standards ..................................................................................................... 4–24
Contents
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