EP1S20F780I6N Altera, EP1S20F780I6N Datasheet - Page 693

• Manufacturer Part Number: EP1S20F780I6N
• Description: IC STRATIX FPGA 20K LE 780-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S20F780I6N

• Number Of Logic Elements/cells: 18460
• Number Of Labs/clbs: 1846
• Total Ram Bits: 1669248
• Number Of I /o: 586
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 18460
• # I/os (max): 586
• Frequency (max): 450.05MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 18460
• Ram Bits: 1669248
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
July 2005
Notes to
(1)
(2)
Size (bits)
Parity bits
Byte enable
True dual-port
mode
Embedded shift
register
Dedicated
content-
addressable
memory (CAM)
support
Pre-loadable
initialization with a
.mif
Packed mode
Feed-through
behavior
Output power-up
condition
Table 10–4. Stratix & Stratix GX TriMatrix Memory Blocks vs. APEX II & APEX 20K ESBs
(1)
Features
.mif: Memory Initialization File.
Packed mode refers to combining two single-port RAM blocks into a single RAM block that is placed into true
dual-port mode.
Table
(2)
10–4:
576
Yes
No
No
Yes
No
Yes
No
Rising edge
Powers up
cleared even if
using a .mif
M512 RAM
Table 10–4
Stratix and Stratix GX TriMatrix memory blocks only support pipelined
mode, while APEX II and APEX 20K ESBs support both pipelined and
flow-through modes. Since all TriMatrix memory blocks can be
pipelined, all input data and address lines are registered, while outputs
can be either registered or combinatorial. You can use Stratix and
Stratix GX memory block registers to implement input and output
registers without utilizing additional resources. You can compile designs
containing pipelined memory blocks (inputs registered) for Stratix and
Stratix GX devices without any modifications. However, if an APEX II or
(1)
Stratix & Stratix GX
4,608
Yes
Yes
Yes
Includes support
for mixed width
Yes
No
Yes
Yes
Rising edge
Powers up
cleared even if
using a .mif
M4K RAM
compares TriMatrix memory with ESBs.
Transitioning APEX Designs to Stratix & Stratix GX Devices
(1)
589,824
Yes
Yes
Yes
Includes support
for mixed width
No
No
No
No
Rising edge
Powers up with
unknown state
M-RAM
Stratix Device Handbook, Volume 2
4,096
No
No
Yes
Includes support
for mixed width
No
Yes
Yes
Yes
Falling edge
Powers up
cleared or to
initialized value,
if using a .mif
APEX II ESB
(1)
2,048
No
No
No
No
Yes
Yes
Yes
Falling edge
Powers up
cleared or to
initialized value,
if using a .mif
APEX 20K ESB
10–9
(1)